Datasheet

56F807 Technical Data Technical Data, Rev. 16
26 Freescale Semiconductor
Figure 3-3 Signal States
Table 3-5 Flash Memory Truth Table
Mode
XE
1
1. X address enable, all rows are disabled when XE=0
YE
2
2. Y address enable, YMUX is disabled when YE=0
SE
3
3. Sense amplifier enable
OE
4
4. Output enable, tri-state Flash data out bus when OE=0
PROG
5
5. Defines program cycle
ERASE
6
6. Defines erase cycle
MAS1
7
7. Defines mass erase cycle, erase whole block
NVSTR
8
8. Defines non-volatile store cycle
Standby L L L L L L L L
Read HHHH L L L L
Word Program H H L L H L L H
Page Erase H L L L L H L H
Mass Erase H L L L L H H H
Table 3-6 IFREN Truth Table
Mode IFREN=1 IFREN=0
Read Read information block Read main memory block
Word program Program information block Program main memory block
Page erase Erase information block Erase main memory block
Mass erase Erase both block Erase main memory block
Data Invalid State
Data1
Data2 Valid
Data
Tri-stated
Data3 Valid
Data2 Data3
Data1 Valid
Data Active Data Active