Datasheet

56F807 Technical Data Technical Data, Rev. 16
Freescale Semiconductor 3
56F807 Block Diagram
JTAG/
OnCE
Port
Digital Reg
Analog Reg
Low Voltage
Supervisor
Program Controller
and
Hardware Looping Unit
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Address
Generation
Unit
Bit
Manipulation
Unit
PLL
Clock Gen
16-Bit
56800
Core
PAB
PDB
XDB2
CGDB
XAB1
XAB2
XTAL
EXTAL
INTERRUPT
CONTROLS
IPBB
CONTROLS
IPBus Bridge
(IPBB)
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
COP RESET
RESET
IRQA
IRQB
Applica-
tion-Specific
Memory &
Peripherals
Interrupt
Controller
Program Memory
61440 x 16 Flash
2048 x 16 SRAM
Boot Flash
2048 x 16 Flash
Data Memory
8192 x 16 Flash
4096 x 16 SRAM
COP/
Watchdog
SPI
or
GPIO
SCI0
or
GPIO
Quad Timer D
/ Alt Func
Quad Timer C
A/D1
A/D2
ADCA
4
2
4
4
4
4
6
PWM Outputs
Fault Inputs
PWMA
16 16
VCAPC V
DD
V
SS
V
DDA
V
SSA
6
28 10*3
•
•
•
•
•
•
•
•
EXTBOOT
Current Sense Inputs
3
Quadrature
Decoder 0
/Quad Timer
CAN 2.0A/B
2
CLKO
External
Address Bus
Switch
Bus
Control
External
Data Bus
Switch
External
Bus
Interface
Unit
RD Enable
WR Enable
DS Select
PS Select
10
16
6
A[00:05]
D[00:15]
A[06:15] or
GPIO-E2:E3 &
GPIO-A0:A7
4
4
6
PWM Outputs
Fault Inputs
PWMB
Current Sense Inputs
3
Quadrature
Decoder 1
/Quad Timer B
4
2
SCI1
or
GPIO
2
Dedicated
GPIO
14
VPP
RSTO
A/D1
A/D2
ADCB
4
4
3
VREF2
VREF
*includes TCS pin which is reserved for factory use and is tied to VSS
56F807 General Description
• Up to 40 MIPS at 80MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Hardware DO and REP loops
• MCU-friendly instruction set supports both DSP
and controller functions: MAC, bit manipulation
unit, 14 addressing modes
• 60K × 16-bit words (120KB) Program Flash
•2K × 16-bit words (4KB) Program RAM
•8K × 16-bit words (16KB) Data Flash
•4K × 16-bit words (8KB) Data RAM
•2K × 16-bit words (4KB) Boot Flash
• Up to 64K × 16- bit words (128KB) each of external
Program and Data memory
• Two 6 channel PWM Modules
• Four 4 channel, 12-bit ADCs
• Two Quadrature Decoders
• CAN 2.0 B Module
• Two Serial Communication Interfaces (SCIs)
• Serial Peripheral Interface (SPI)
• Up to four General Purpose Quad Timers
• JTAG/OnCE
TM
port for debugging
• 14 Dedicated and 18 Shared GPIO lines
• 160-pin LQFP or 160 MAPBGA Packages