Datasheet

56F807 Technical Data Technical Data, Rev. 16
32 Freescale Semiconductor
3.4.4 Phase Locked Loop Timing
Table 3-9 PLL Timing
Operating Conditions: V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40° to +85°C
Characteristic Symbol Min Typ Max Unit
External reference crystal frequency for the PLL
1
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.2.
f
osc
4810MHz
PLL output frequency
2
2. ZCLK may not exceed 80MHz. For additional information on ZCLK and f
out
/2, please refer to the OCCS chapter in the
User Manual. ZCLK = f
op
f
out
/2 40 — 110 MHz
PLL stabilization time
3
0
o
to +85
o
C
3. This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
t
plls
—110ms
PLL stabilization time
3
-40
o
to 0
o
C
t
plls
— 100 200 ms