Datasheet

Quad Timer Timing
56F807 Technical Data Technical Data, Rev. 16
Freescale Semiconductor 41
3.8 Quad Timer Timing
Figure 3-23 Timer Timing
Table 3-13 Timer Timing
1, 2
Operating Conditions: V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40° to +85°C, C
L
≤ 50pF, f
OP
= 80MHz
1. In the formulas listed, T = the clock cycle. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
Characteristic Symbol Min Max Unit
Timer input period P
IN
4T + 6 — ns
Timer input high/low period P
INHL
2T + 3 — ns
Timer output period P
OUT
2T — ns
Timer output high/low period P
OUTHL
1T — ns
P
OUT
P
OUTHL
P
OUTHL
P
IN
P
INHL
P
INHL
Timer Inputs
Timer Outputs