Datasheet

JTAG Timing
56F807 Technical Data Technical Data, Rev. 16
Freescale Semiconductor 47
Figure 3-30 Test Access Port Timing Diagram
Figure 3-31 TRST Timing Diagram
Figure 3-32 OnCE—Debug Event
Input Data Valid
Output Data Valid
Output Data Valid
t
DS
t
DH
t
DV
t
TS
t
DV
TCK
(Input)
TDI
(Input)
TDO
(Output)
TDO
(Output
)
TDO
(Output)
TMS
TRST
(Input)
t
TRST
DE
t
DE