Freescale Semiconductor Data Sheet: Technical Data Document Number: FXOS8700CQ Rev. 4.0, 03/2014 An Energy-Efficient Solution by Freescale Xtrinsic FXOS8700CQ 6-Axis Sensor with Integrated Linear Accelerometer and Magnetometer FXOS8700CQ FXOS8700CQ is a small, low-power, 3-axis linear accelerometer and 3-axis magnetometer combined into a single package.
Applications • E-Compass in mobile devices • User interface (menu scrolling by orientation change, tap detection for button replacement) • Orientation detection (portrait/landscape: up/down, left/right, back/front orientation identification) • Augmented reality (AR), gaming, and real-time activity analysis (pedometry, freefall, and drop detection for hard disk drives and other devices) • Power management for mobile devices using inertial and magnetic event detection • Shock and vibration monitoring
Contents 1 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3 Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.1 TEMP (0x51) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 Accelerometer output data registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.
10.15 Magnetometer offset correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.15.1 M_OFF_X_MSB (0x3F), M_OFF_X_LSB (0x40), M_OFF_Y_MSB (0x41), M_OFF_Y_LSB (0x42), M_OFF_Z_MSB (0x43), M_OFF_Z_LSB (0x44) registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.16 Magnetometer threshold function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FXOS8700CQ 6 Sensors Freescale Semiconductor, Inc.
1 Block Diagram Figure 1. Block diagram FXOS8700CQ Sensors Freescale Semiconductor, Inc.
RST N/C VDD Pin Description 16 15 14 VDDIO 1 13 Reserved BYP 2 12 GND Reserved 3 11 INT1 SCL/SCLK 4 10 SA1/CS_B GND 5 9 INT2 6 7 8 SA0/MISO Crst FXOS8700CQ SDA/MOSI 2 Top View 16 Lead QFN-COL 3 mm x 3 mm x 1.2 mm Figure 2. Pinout diagram Table 1.
The digital control signals SCL, SDA, SA0, SA1, and RST are not tolerant of voltages exceeding VDDIO + 0.3 V. If VDDIO is removed, these pins will clamp any logic signals through their internal ESD protection diodes. The function and timing of the two interrupt pins (INT1 and INT2) are user programmable through the I2C/SPI interface. The SDA and SCL I2C connections are open drain and therefore require a pullup resistor as shown in the application diagram in Figure 3.
2.2 Orientation Top view Side view BOTTOM Pin 1 Xout @ 0 g Yout @ 0 g Zout @ -1 g Xout @ 0 g Yout @ -1 g Zout @ 0 g Maximum My Maximum Mz TOP Earth Gravity Magnetic Field Xout @ 0 g Yout @ 0 g Zout @ 1 g Xout @ -1 g Yout @ 0 g Zout @ 0 g Xout @ 1 g Yout @ 0 g Zout @ 0 g Maximum Mx Minimum Mx Minimum Mz +Az, +Mz +Ax, +Mx 1 Xout @ 0 g Yout @ 1 g Zout @ 0 g Minimum My +Ay, +My Top view Figure 4. Product orientation and axis orientation FXOS8700CQ 10 Sensors Freescale Semiconductor, Inc.
3 Terminology 3.1 Sensitivity Sensitivity is represented in mg/LSB for the accelerometer and μT/LSB for the magnetometer. The magnetometer sensitivity is fixed at 0.1 μT/LSB. The accelerometer sensitivity changes with the full-scale range selected by the user. Accelerometer sensitivity is 0.244 mg/LSB in 2 g mode, 0.488 mg/LSB in 4 g mode, and 0.976 mg/LSB in 8 g mode. 3.
4 Device Characteristics 4.1 Mechanical characteristics (accelerometer) Table 2. Mechanical characteristics @ VDD = 2.5 V, VDDIO = 1.8 V T = 25 °C unless otherwise noted. Parameter Test Conditions Symbol Min Measurement range(1) ±4 g mode ±4 g mode SENACC ±8 g mode Sensitivity change with temperature Sensitivity accuracy Unit g ±8 ±2 g mode (1) Max ±4 FSACC ±8 g mode Sensitivity Typ ±2 ±2 g mode 4096 LSB/g 0.244 mg/LSB 2048 LSB/g 0.488 mg/LSB 1024 LSB/g 0.
4.2 Magnetic characteristics (magnetometer) Table 3. Magnetic characteristics @ VDD = 2.5 V, VDDIO = 1.8 V T = 25 °C unless otherwise noted. Parameter Test Conditions Measurement range Symbol Min FSMAG ±1200 Typ Max Unit μT SENMAG 0.1 μT/LSB Sensitivity change versus temperature TCSMAG ±0.1 %/°C Zero-flux offset accuracy(1) OFFMAG ±10 μT Zero-flux offset change with temperature TCOMAG ±0.8 μT/°C Hysteresis(2)(3) HYSTMAG ±0.5 %FSMAG ±1 %FSMAG 0.
4.4 Electrical characteristics Table 5. Electrical characteristics @ VDD = 2.5 V, VDDIO = 1.8 V T = 25 °C unless otherwise noted. Parameter Test Conditions Supply voltage Interface supply voltage Symbol Min Typ Max Unit VDD 1.95 2.5 3.6 V VDDIO 1.62 1.8 3.6 V 8 ODR = 12.
Values in the following table are based on limited number of samples and are for reference only. Output data rates do not exist for the shaded cells. Table 6. IDD (µA) table versus operating modes (VDD + VDDIO), VDD = VDDIO = 2.
4.5 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Freescale recommends that customers using magnetic sensor components adopt industry standard safe handling practices and procedures for magnetic products.
5 Digital Interfaces 5.1 I2C interface characteristics Table 9. I2C slave timing values(1) Parameter I2C Fast Mode Symbol Unit Min Max 400 SCL Clock Frequency fSCL 0 Bus Free Time between STOP and START condition tBUF 1.3 μs (Repeated) START Hold Time tHD;STA 0.6 μs (Repeated) START Setup Time tSU;STA 0.6 μs STOP Condition Setup Time tSU;STO 0.6 SDA Data Hold Time SDA Valid Time SDA Valid Acknowledge Time (4) μs (2) μs tVD;DAT 0.9(2) μs tVD;ACK 0.9(2) μs 0.
5.1.1 General I2C operation There are two signals associated with the I2C bus: the Serial Clock Line (SCL) and the Serial Data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. External pullup resistors connected to VDDIO are required for SDA and SCL. When the bus is free both the lines are high. The I2C interface is compliant with fast mode (400 kHz), and normal mode (100 kHz) I2C standards.
Multiple-byte write The FXOS8700CQ automatically increments the register address write pointer after a write command is received. Therefore, after following the steps of a single-byte write, multiple bytes of data can be written to sequential registers after each FXOS8700CQ acknowledgment (ACK) is received.
5.2 SPI Interface characteristics SPI interface is a classical master/slave serial port. The FXOS8700CQ is always considered as the slave and thus is never initiating the communication. Table 11 and Figure 7 describe the timing requirements for the SPI system. Table 11.
The FXOS8700CQ SPI configuration is as follows: • • • Polarity: rising/falling Phase: sample/setup Order: MSB first Data is sampled during the rising edge of SCLK and set up during the falling edge of SCLK. 5.2.2 SPI READ/WRITE operations A READ operation is initiated by transmitting a 0 for the R/W bit. Then the 8-bit register address, ADDR[7:0] is encoded in the first and second serialized bytes. Subsequent bits are ignored by the part. The read data is deserialized from the MISO pin.
6 Modes of Operation Sleep Active OFF Standby Wake Figure 9. FXOS8700CQ power mode transition diagram Table 14. Mode of operation description Mode OFF I2C/SPI Bus state Powered down VDD VDDIO <1.8 V VDDIO can be > VDD Function description The device is powered off. All analog and digital blocks are shutdown. I2C bus inhibited. Standby I2C/SPI communication with FXOS8700CQ is possible ON VDDIO = High VDD = High Active bit is cleared Only digital blocks are enabled.
7 Embedded Functionality FXOS8700CQ is a low-power, digital output, 6-axis sensor with both I2C and SPI interfaces. Extensive embedded functionality is provided to detect inertial and magnetic events at low power, with the ability to notify the host processor of an event using either of the two programmable interrupt pins.
7.4 Auto-Wake/Sleep mode FXOS8700CQ can be configured to transition between sample rates (with their respective current consumptions) based on the status of the embedded interrupt event generators in the device. The advantage of using the Auto-Wake/Sleep is that the system can automatically transition to a higher sample rate (higher current consumption) when needed but spends the majority of the time in the Sleep mode (lower current) when the device does not require higher sampling rates.
7.8 Pulse detection FXOS8700CQ has embedded single/double and directional pulse detection. This function employs several timers for programming the pulse width time and the latency between pulses. The detection thresholds are independently programmable for each axis. The acceleration data input to the pulse detection circuit can be put through both high and low-pass filters, allowing for greater flexibility in discriminating between pulse and tap events.
8 Register Map Table 15.
Table 15.
Table 15.
Table 15.
Table 15.
9 Example FXOS8700CQ Driver Code 9.1 Introduction It is very straightforward to configure the FXOS8700CQ and start receiving data from the three accelerometer and three magnetometer channels. Unfortunately, since every hardware platform will be different, it is not possible to provide completely portable software drivers. This section therefore provides real FXOS8700CQ driver code for a Kinetis uC board running under the MQX operating system.
9.4 FXOS8700CQConfiguration function This function configures the FXOS8700CQ for 200-Hz hybrid mode meaning that both accelerometer and magnetometer data are provided at the 200-Hz rate.The code is self-explanatory and can be easily customized for different settings. Example 5.
if (s_i2c_write_regs(aFP, FXOS8700CQ_SLAVE_ADDR, FXOS8700CQ_M_CTRL_REG2, &databyte, (uint8_t) 1) != 1) { return (I2C_ERROR); } // write 0000 0001= 0x01 to XYZ_DATA_CFG register // [7]: reserved // [6]: reserved // [5]: reserved // [4]: hpf_out=0 // [3]: reserved // [2]: reserved // [1-0]: fs=01 for accelerometer range of +/-4g range with 0.
{ // copy the 14 bit accelerometer byte data into 16 bit words pAccelData->x = (int16_t)(((Buffer[1] << 8) | Buffer[2]))>> 2; pAccelData->y = (int16_t)(((Buffer[3] << 8) | Buffer[4]))>> 2; pAccelData->z = (int16_t)(((Buffer[5] << 8) | Buffer[6]))>> 2; // copy the magnetometer byte data into 16 bit words pMagnData->x = (Buffer[7] << 8) | Buffer[8]; pMagnData->y = (Buffer[9] << 8) | Buffer[10]; pMagnData->z = (Buffer[11] << 8) | Buffer[12]; } else { // return with error return (I2C_ERROR); } // normal return
10 Registers by Functional Blocks 10.1 Device configuration 10.1.1 STATUS (0x00) register Table 16. STATUS register DR_STATUS or F_STATUS 0 0 0 0 0 0 0 0 Table 17.
Table 19. DR_STATUS description (Continued) zyxdr zyxdr signals that a new acquisition for any of the enabled channels is available. zyxdr is cleared when the high-bytes of the acceleration data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) are read. X, Y, Z-axis new data ready. 0: No new set of data ready 1: New set of data is ready zdr zdr is set to 1 whenever a new Z-axis data acquisition is completed. zdr is cleared anytime the OUT_Z_MSB register is read. Z-axis new data available.
10.1.4 TRIG_CFG (0x0A) register FIFO trigger configuration register. After the interrupt flag of the enabled event in TRIG_CFG is set, the FIFO (when configured in Trigger mode) is gated at the time of the interrupt event preventing the further collection of data samples. This allows the host processor to analyze the data leading up to the event detection (up to 32 samples).
10.1.6 INT_SOURCE (0x0C) register Interrupt source register. The bits that are set (logic ‘1’) indicate which function has asserted its interrupt and conversely bits that are cleared (logic ‘0’) indicate which function has not asserted its interrupt. Additional interrupt flags for magnetic interrupt events are located in the M_INT_SRC register (0x5E).
10.1.7 WHO_AM_I (0x0D) register Table 29. WHO_AM_I register who_am_i[7:0] 0xC7 Device identification register. This register contains the device identifier which is set to 0xC4 for preproduction devices and 0xC7 for production devices. 10.1.8 CTRL_REG1 (0x2A) register NOTE Except for Standby mode selection, the device must be in Standby mode to change any of the fields within CTRL_REG1 (0x2A). Table 30. CTRL_REG1 register aslp_rate[1:0] dr[2:0] lnoise f_read active 0b00 0b001 0 0 0 Table 31.
Table 33. System Output Data Rate selection dr[2] dr[1] dr[0] ODR accelerometer or Period accelerometer or ODR hybrid mode (Hz) Period hybrid mode (ms) magnetometer only modes (Hz) magnetometer only modes (ms) 0 0 0 800.0 1.25 400 2.5 0 0 1 400.0 2.5 200 5 0 1 0 200.0 5 100 10 0 1 1 100.0 10 50 20 1 0 0 50.0 20 25 80 1 0 1 12.5 80 6.25 160 1 1 0 6.25 160 3.125 320 1 1 1 1.5625 640 0.
Table 35. CTRL_REG2 bit descriptions mods[1:0] Accelerometer Wake mode OSR mode selection. This setting, along with the ODR selection (CTRL_REG1[dr]) determines the Wake mode power and noise for acceleration measurements. See Table 36 and Table 37 for more information. 1. When slpe = 1, a transition between Sleep mode and Wake mode (or vice-versa) results in a FIFO flush and resets all of the internal functions debounce counters.
10.1.10 CTRL_REG3 [Interrupt Control Register] (0x2C) register Table 38. CTRL_REG3 register fifo_gate wake_trans wake_lndprt wake_pulse wake_ffmt wake_a_vecm ipol pp_od 0 0 0 0 0 0 0 0 Table 39. CTRL_REG3 bit descriptions Field Description fifo_gate 0: FIFO gate is bypassed. FIFO is flushed upon the system mode transitioning from Wake-to-Sleep mode or from Sleepto-Wake mode.
10.1.11 CTRL_REG4 [Interrupt Enable Register] (0x2D) register Table 40. CTRL_REG4 register int_en_aslp int_en_fifo int_en_trans int_en_lndprt int_en_pulse int_en_ffmt int_en_a_vecm int_en_drdy 0 0 0 0 0 0 0 0 Table 41.
10.1.12 CTRL_REG5 [Interrupt Routing Configuration Register] (0x2E) register Table 42. CTRL_REG5 register int_cfg_aslp int_cfg_fifo int_cfg_trans int_cfg_lndprt int_cfg_pulse int_cfg_ffmt int_cfg_a_vecm int_cfg_drdy 0 0 0 0 0 0 0 0 Table 43.
Data Ready Freefall/Motion Detection Pulse Detection Orientation Detection INT1 Transient Acceleration Detection INTERRUPT CONTROLLER Auto-Sleep Acceleration Vector-magnitude INT2 Magnetic Vector-magnitude Magnetic Threshold Detection FIFO Interrupt 9 9 INT ENABLE INT CFG Figure 10. Interrupt controller block diagram The system’s interrupt controller uses the corresponding bit field in the CTRL_REG5 register to determine the routing for the INT1 and INT2 interrupt pins.
10.2 Auto-Sleep trigger 10.2.1 ASLP_COUNT (0x29) register The ASLP_COUNT register sets the minimum time period of event flag inactivity required to initiate a change from the current active mode ODR value specified in CTRL_REG1[dr] to the Sleep mode ODR value specified in CTRL_REG1[aslp_rate], provided that CTRL_REG2[slpe] = 1. See Table 47 for functional blocks that may be monitored for inactivity in order to trigger the return-to-sleep event. Table 44.
If any of the interrupt sources listed under the Return-to-Sleep column is asserted before the sleep counter reaches the value specified in ASLP_COUNT, then all sleep mode transitions are terminated and the internal sleep counter is reset. If none of the interrupts listed under the Return-to-Sleep column are asserted within the time limit specified by the ASLP_COUNT register, the system will transition to the Auto-Sleep mode and use the ODR value specified in CTRL_REG1[aslp_rate].
10.4 Accelerometer output data registers 10.4.1 OUT_X_MSB (0x01), OUT_X_LSB (0x02), OUT_Y_MSB (0x03), OUT_Y_LSB (0x04), OUT_Z_MSB (0x05), OUT_Z_LSB (0x06) registers These registers contain the X-axis, Y-axis, and Z-axis 14-bit left-justified sample data expressed as 2's complement numbers.
10.5 Accelerometer FIFO 10.5.1 F_SETUP (0x09) register Table 55. F_SETUP register f_mode[1:0] f_wmrk[5:0] 0 0b00_0000 Table 56. F_SETUP bit descriptions Field Description f_mode[1:0](1)(2)(3) FIFO buffer operating mode. 0b00: FIFO is disabled. 0b01: FIFO contains the most recent samples when overflowed (circular buffer). Oldest sample is discarded to be replaced by new sample. 0b10: FIFO stops accepting new samples when overflowed. 0b11: FIFO trigger mode.
10.6 Accelerometer sensor data configuration 10.6.1 XYZ_DATA_CFG (0x0E) register The XYZ_DATA_CFG register is used to configure the desired acceleration full-scale range, and also to select whether the output data is passed through the high-pass filter. Table 57. XYZ_DATA_CFG register — — — hpf_out — — fs[1:0] 0 0 0 0 0 0 0b00 Example 7. Table 58.
Table 62. HP_FILTER_CUTOFF High-Pass cutoff frequency (Hz) sel = 0b00 ODR (Hz) sel = 0b01 Normal LPLN High resolution Low power Normal LPLN High resolution Low power 800 16 16 16 16 8 8 8 8 400 16 16 16 8 8 8 8 4 200 8 8 16 4 4 4 8 2 100 4 4 16 2 2 2 8 1 50 2 2 16 1 1 1 8 0.5 12.5 2 0.5 16 0.25 1 0.25 8 0.125 6.25 2 0.25 16 0.125 1 0.125 8 0.063 1.56 2 0.063 16 0.031 1 0.031 8 0.
10.8 Portrait/Landscape Detection The FXOS8700CQ is capable of detecting six orientations: Landscape Left, Landscape Right, Portrait Up, and Portrait Down with Z-lockout feature as well as Face Up and Face Down orientation as shown in Figures 13, 14 and 15. For more details on the meaning of the different user-configurable settings and for example code, please refer to Freescale application note AN4068. 90° NORMAL DETECTION Z-LOCK = 32.142° LOCKOUT REGION 0° Figure 13.
10.8.1 PL_STATUS (0x10) register This status register can be read to get updated information on any change in orientation by reading bit 7, or the specifics of the orientation by reading the other bits. For further understanding of Portrait Up, Portrait Down, Landscape Left, Landscape Right, Back and Front orientations please refer to Figure 15. The interrupt is cleared when reading the PL_STATUS register. Table 63. PL_STATUS register newlp lo — — — lapo[1:0] bafro 0 0 0 0 0 0b00 0 Table 64.
10.8.2 PL_CFG (0x11) register This register enables the Portrait/Landscape function and sets the behavior of the debounce counter. Table 65. PL_CFG register dbcntm pl_en — — — — — — 1 0 0 0 0 0 0 0 Table 66. PL_CFG bit descriptions Field Description Debounce counter mode selection. 0: Decrements debounce whenever condition of interest is no longer valid. 1: Clears counter whenever condition of interest is no longer valid. dbcntm Portrait/Landscape detection enable.
10.8.4 PL_BF_ZCOMP (0x13) register Back/Front and Z-tilt angle compensation register Table 69. PL_BF_ZCOMP register bkfr[1:0] — — — zlock[2:0] 0b10 0 0 0 0b100 Table 70. PL_BF_ZCOMP bit descriptions Field Description zlock[2:0] Z-lock angle threshold. range is from approximately 13° to 44°. Step size is approximately 4°. See Table 71 for more information. Default value: 0x04 → ∼28°. Maximum value: 0x07 → ~44°. bkfr[1:0] Back/front trip angle threshold. See Table 72 for more information.
10.8.5 PL_THS_REG (0x14) register Portrait to landscape trip threshold registers. Table 73. PL_THS_REG register pl_ths[4:0] hys[2:0] 0b0_1000 0b100 Table 74. Threshold angle lookup table pl_ths[4:0] value Threshold angle (approx.) 0x07 15° 0x09 20° 0x0C 30° 0x0D 35° 0x0F 40° 0x10 45° 0x13 55° 0x14 60° 0x17 70° 0x19 75° Table 75.
A_FFMT_SRC[a_ffmt_ea] flag can only be cleared by reading the A_FFMT_SRC register. When A_FFMT_CFG[a_ffmt_ele] = 0, freefall or motion events are not latched, and the A_FFMT_SRC[a_ffmt_ea] bit reflects the real-time status of the event detection. A_FFMT_THS[a_ffmt_dbcntm] bit determines the debounce filtering behavior of the logic which sets the A_FFMT_SRC[a_ffmt_ea] bit. See Figure 17 for details.
10.9.2 A_FFMT_SRC (0x16) register Freefall/motion source register. Read-only register. This register keeps track of the acceleration event which is triggering (or has triggered, in case of A_FFMT_CFG[a_ffmt_ele] = 1) the event flag. In particular A_FFMT_SRC[a_ffmt_ea] is set to a logic ‘1’ when the logical combination of acceleration event flags specified in A_FFMT_CFG register is true.
10.9.3 A_FFMT_THS (0x17), A_FFMT_ THS_X_MSB (0x73), A_FFMT_THS_X_LSB (0x74), A_FFMT_THS_Y_MSB (0x75), A_FFMT_THS_Y_LSB (0x76), A_FFMT_THS_Z_MSB (0x77), A_FFMT_THS_Z_LSB (0x78) registers Freefall/motion detection threshold registers. Table 81. A_FFMT_THS (0x17) register a_ffmt_dbcntm ths[6:0] 0 0b000_0000 Table 82.
Table 88. A_FFMT_THS_Z_MSB (0x77) register — a_ffmt_ths_z[12:6] 0 0b000_0000 Table 89. A_FFMT_THS_Z_LSB (0x78) register a_ffmt_ths_z[5:0] — — 0b00_0000 0 0 +Full Scale X, Y, Z High-g Region High-g Positive Threshold (Motion OR of enabled axes) Positive Acceleration Low-g Threshold (Freefall - AND of enabled axes) X, Y, Z Low-g Region High-g Negative Threshold (Motion - OR of enabled axes) X, Y, Z High-g Region Negative Acceleration -Full Scale Figure 16.
Table 92. A_FFMT_COUNT relationship with the ODR Max time range (s) ODR (Hz) Time step (ms) Low power Normal LPLN High resolution LP 1.25 1.25 Normal LPLN High resolution 800 0.319 0.319 0.319 0.319 1.25 1.25 400 0.638 0.638 0.638 0.638 2.5 2.5 2.5 2.5 200 1.28 1.28 0.638 1.28 5 5 2.5 5 100 2.55 2.55 0.638 2.55 10 10 2.5 10 50 5.1 5.1 0.638 5.1 20 20 2.5 20 12.5 5.1 20.4 0.638 20.4 20 80 2.5 80 6.25 5.1 20.4 0.638 40.8 20 80 2.5 160 1.
10.10 Accelerometer vector-magnitude function The accelerometer vector-magnitude function is an inertial event detection function available to assist host software algorithms in detecting motion events. 2 2 2 If ( a_x_out – a_x_ref ) + ( a_y_out – a_y_ref ) + ( a_z_out – a_z_ref ) > A_VECM_THS for a time period greater than the value stored in A_VECM_CNT, the vector-magnitude change event flag is triggered.
10.10.2 A_VECM_THS_MSB (0x60) register Table 95. A_VECM_THS_MSB register a_vecm_dbcntm — — a_vecm_ths[12:8] 0 0 0 0b0_0000 Table 96. A_VECM_THS_MSB bit descriptions Field Description a_vecm_dbcntm Control bit a_vecm_dbcntm defines how the debounce timer is reset when the condition for triggering the interrupt is no longer true. When a_vecm_dbcntm = 0 the debounce counter is decremented by 1 when the vector-magnitude result is below the programmed threshold value.
10.10.5 A_VECM_INITX_MSB (0x63) register Table 100. A_VECM_INITX_MSB register — — a_vecm_initx[13:8] 0 0 0b00_0000 Table 101. A_VECM_INITX_MSB bit description Field Description Most significant 6 bits of the signed 14-bit initial X-axis value to be used as ref_x when A_VECM_CFG[a_vecm_initm] = 1. a_vecm_initx[13:8] The resolution is determined by the settings made in XYZ_DATA_CFG[fs], and is equal to the accelerometer resolution. 10.10.6 A_VECM_INITX_LSB (0x64) register Table 102.
Table 109. A_VECM_INITZ_MSB bit description Field Description a_vecm_initz[13:8] Most significant 6 bits of the signed 14-bit initial Z-axis value to be used as ref_z when A_VECM_CFG[a_vecm_initm] = 1. The resolution is determined by the settings made in XYZ_DATA_CFG[fs], and is equal to the accelerometer resolution. 10.10.10 A_VECM_INITZ_LSB (0x68) register Table 110. A_VECM_INITZ_LSB register a_vecm_initz[7:0] 0b0000_0000 Table 111.
10.11.2 TRANSIENT_SRC (0x1E) register Transient event flag source register. This register provides the event status of the enabled axes and polarity (directional) information. Table 114. TRANSIENT_ CFG register — tran_ea tran_zef tran_zpol tran_yef tran_ypol tran_xef trans_xpol 0 0 0 0 0 0 0 0 Table 115. TRANSIENT_SRC bit descriptions Field Description tran_ea Transient event active flag. 0: No transient event active flag has been asserted.
10.11.3 TRANSIENT_THS (0x1F) register The TRANSIENT_THS register determines the debounce counter behavior and also sets the transient event detection threshold.It is possible to use A_FFMT_THS_X/Y/Z MSB and LSB registers to set transient acceleration thresholds for individual axes using the a_ffmt_trans_ths_en bit in A_FFMT_THS_Y_MSB register. Table 116. TRANSIENT_THS register tr_dbcntm tr_ths[6:0] 0 0b000_0000 Table 117.
10.12 Pulse detection 10.12.1 PULSE_CFG (0x21) register This register configures the pulse event detection function. Table 121. PULSE_CFG register pls_dpa pls_ele pls_zdpefe pls_zspefe pls_ydpefe pls_yspefe pls_xdpefe pls_xspefe 0 0 0 0 0 0 0 0 Table 122. PULSE_CFG bit descriptions Field Description pls_dpa Double-pulse abort. 0: Double-pulse detection is not aborted if the start of a pulse is detected during the time period specified by the PULSE_LTCY register.
10.12.2 PULSE_SRC (0x22) register This register indicates the status bits for the pulse detection function. Table 123. PULSE_SRC register pls_src_ea pls_src_axz pls_src_axy pls_src_axx pls_src_dpe pls_src_polz pls_src_poly pls_src_polx Table 124. PULSE_SRC bit descriptions Field Description pls_src_ea Event active flag. 0: No interrupt has been generated 1: One or more interrupt events have been generated pls_src_axz Z-axis event flag. 0: No interrupt.
10.12.4 PULSE_THSY (0x24) register Table 127. PULSE_THSY register — pls_thsy[6:0] 0 0b000_0000 Table 128. PULSE_THSY bit description Field pls_thsy[6:0] Description Pulse threshold for Y-axis. 10.12.5 PULSE_THSZ (0x25) register Table 129. PULSE_THSZ register — pls_thsz[6:0] 0 0b000_0000 Table 130. PULSE_THSZ bit description Field pls_thsz[6:0] Description Pulse threshold for Z-axis. 10.12.6 PULSE_TMLT (0x26) register Table 131. PULSE_TMLT register pls_tmlt[7:0] 0b0000_0000 Table 132.
Table 134. Time step for PULSE_TMLT with HP_FILTER_CUTOFF[pls_hpf_en] = 0 Max time range (s) ODR (Hz) Time step (ms) Low power Normal LPLN High resolution Low power Normal LPLN High resolution 800 0.159 0.159 0.159 0.159 0.625 0.625 0.625 0.625 400 0.159 0.159 0.159 0.319 0.625 0.625 0.625 1.25 200 0.319 0.319 0.159 0.638 1.25 1.25 0.625 2.5 100 0.638 0.638 0.159 1.28 2.5 2.5 0.625 5 50 1.28 1.28 0.159 2.55 5 5 0.625 10 12.5 1.28 5.1 0.159 10.
Table 138. Time step for PULSE_LTCY with HP_FILTER_CUTOFF[pls_hpf_en] = 0 Max time range (s) ODR (Hz) Time step (ms) Low power Normal LPLN High resolution Low power Normal LPLN High resolution 800 0.318 0.318 0.318 0.318 1.25 1.25 1.25 1.25 400 0.318 0.318 0.318 0.638 1.25 1.25 1.25 2.5 200 0.638 0.638 0.318 1.276 2.5 2.5 1.25 5 100 1.276 1.276 0.318 2.56 5 5 1.25 10 50 2.56 2.56 0.318 5.1 10 10 1.25 20 12.5 2.56 10.2 0.318 20.4 10 40 1.25 80 6.
Table 142. Time step for PULSE_WIND with HP_FILTER_CUTOFF[pls_hpf_en] = 0 Max time range (s) ODR (Hz) Time step (ms) Low power Normal LPLN High resolution Low power Normal LPLN High resolution 800 0.318 0.318 0.318 0.318 1.25 1.25 1.25 1.25 400 0.318 0.318 0.318 0.638 1.25 1.25 1.25 2.5 200 0.638 0.638 0.318 1.276 2.5 2.5 1.25 5 100 1.276 1.276 0.318 2.56 5 5 1.25 10 50 2.56 2.56 0.318 5.1 10 10 1.25 20 12.5 2.56 10.2 0.318 20.4 10 40 1.25 80 6.
Table 148. OFF_Z bit description Field off_z[7:0] 10.14 Description Z-axis offset correction value expressed as an 8-bit 2's complement number. Magnetometer data registers 10.14.1 M_DR_STATUS (0x32) register Magnetic data-ready status register. This register indicates the real-time status information of the X, Y, and Z magnetic sample data. Table 149. M_DR_STATUS register xyzow zow yow xow xyzdr zdr ydr xdr 0 0 0 0 0 0 0 0 Table 150.
10.14.2 M_OUT_X_MSB (0x33), M_OUT_X_LSB (0x34), M_OUT_Y_MSB (0x35), M_OUT_Y_LSB (0x36), M_OUT_Z_MSB (0x37), M_OUT_Z_LSB (0x38) registers X-axis, Y-axis, and Z-axis 16-bit magnetic output data expressed as 2's complement numbers, with a resolution of 0.1 μT/LSB. Table 151. M_OUT_X_MSB (0x33) register m_out_x[15:8] 0b0000_0000 Table 152. M_OUT_X_LSB (0x34) register m_out_x[7:0] 0b0000_0000 Table 153. M_OUT_Y_MSB (0x35) register m_out_y[15:8] 0b0000_0000 Table 154.
Table 162. CMP_Z_LSB (0x3E) register cmp_z[7:0] 10.14.4 MAX_X_MSB (0x45), MAX_X_LSB (0x46), MAX_Y_MSB (0x47), MAX_Y_LSB (0x48), MAX_Z_MSB (0x49), MAX_Z_LSB (0x4A) registers The magnetometer MAX_X/Y/Z registers are 16-bit 2's complement format with a resolution of 0.1 μT/LSB. The registers are read/write and along with the MIN_X/Y/Z registers are used to calculate the magnetic offset for each axis using the equation (MAX_X/Y/Z + MIN_X/Y/Z) /2 when M_CTRL_REG2[maxmin_dis] = 0 (default).
10.14.5 MIN_X_MSB (0x4B), MIN_X_LSB (0x4C), MIN_Y_MSB (0x4D), MIN_Y_LSB (0x4E), MIN_Z_MSB (0x4F), MIN_Z_LSB (0x50) registers The magnetometer MIN_X/Y/Z registers are 16-bit, 2's complement format with a resolution of 0.1 μT/LSB. The registers are read/write and along with the MAX_X/Y/Z registers are used to calculate the magnetic offset for each axis using the equation (MAX_X/Y/Z + MIN_X/Y/Z) /2 when M_CTRL_REG2[maxmin_dis] = 0 (default).
10.15 Magnetometer offset correction 10.15.1 M_OFF_X_MSB (0x3F), M_OFF_X_LSB (0x40), M_OFF_Y_MSB (0x41), M_OFF_Y_LSB (0x42), M_OFF_Z_MSB (0x43), M_OFF_Z_LSB (0x44) registers The zero-field output for each axis can be adjusted by writing to these registers. The user must set M_CTRL_REG3[m_raw] = 0 (default) for the values in these registers to have any effect on the magnetic output data.
10.16 Magnetometer threshold function The magnetometer threshold function works in a similar manner to the freefall/motion detection module but uses magnetic data for the event detection instead of acceleration data. The m_ths_oae bit setting determines the logic used to evaluate the threshold detection function for the enabled axes.
+ Full Scale X, Y, Z above threshold X (Y, Z) High(positive) Threshold + Larger Field 0 Field Smaller Field Threshold - X (Y, Z) High (negative) X, Y, Z below threshold -Full Scale Figure 18. Illustration of magnetic threshold detection 10.16.2 M_THS_SRC (0x53) register Magnetic-threshold interrupt source register. This register keeps track of the magnetic threshold event which is triggering (or has triggered, when M_THS_CFG[m_ths_ele] = 1) the event flag.
10.16.3 M_THS_X_MSB (0x54), M_THS_X_LSB (0x55), M_THS_Y_MSB (0x56), M_THS_Y_LSB (0x57), M_THS_Z_MSB (0x58), M_THS_Z_LSB (0x59) registers The M_THS_X/Y/Z registers contain the unsigned 15-bit magnetic thresholds used by the magnetic-threshold function. Each register has a resolution of 0.1 μT/LSB. The thresholds are evaluated after the magnetic data has been adjusted by the offset value stored in the M_OFF_X/Y/Z registers when M_CTRL_REG3[m_raw] = 0. Table 185.
10.16.4 M_THS_COUNT (0x5A) register This register sets the number of debounce sample counts required before a magnetic threshold event is triggered.The behavior of the debounce counter is controlled by M_THS_X_MSB [m_ths_dbcntm]. Table 192. M_THS_COUNT register m_ths_cnt[7:0] 0b0000_0000 Table 193. M_THS_COUNT bit description Field m_ths_cnt[7:0] Description Magnetic threshold debounce count value. When the internal debounce counter reaches the M_THS_COUNT value a magnetic event flag is set.
Magnetic Event Count Threshold (a) FF Counter EA Magnetic Event MAG_THS_X_MSB[m_ths_dbcntm] = 1 Count Threshold (b) Debounce Counter EA Magnetic Event MAG_THS_X_MSB[m_ths_dbcntm] = 0 Count Threshold (c) Debounce Counter EA Figure 19. DBCNTM bit function 10.17 Magnetometer control registers 10.17.1 M_CTRL_REG1 (0x5B) register Table 195. M_CTRL_REG1 register m_acal m_rst m_ost m_os[2:0] m_hms[1:0] 0 0 0 0b000 0b00 Table 196.
Table 196. M_CTRL_REG1 bit descriptions (Continued) One-shot triggered magnetic measurement mode: 0: No action taken, or one-shot measurement complete. 1: If device is in Active mode no action is taken. If device is in Standby mode, take one set of magnetic measurements, clear this bit, and return to Standby mode. m_ost m_os[2:0] Oversample ratio (OSR) for magnetometer data (see Table 201).
10.17.3 M_CTRL_REG3 (0x5D) register Table 199. M_CTRL_REG3 register m_raw m_aslp_os[2:0] m_ths_xyz_update m_st_z m_st_xy[1:0] 0 0b000 0 0 0b00 Table 200. M_CTRL_REG3 bit descriptions Field Description m_raw Magnetic measurement RAW mode enable: 0: Values stored in the M_OFF_X/Y/Z registers are applied to the magnetic sample data. This bit must be cleared in order for the automatic hard-iron compensation function to have any effect.
10.18 Magnetometer vector-magnitude function The magnetometer vector-magnitude function will generate an interrupt when 2 2 2 ( m_x_out – m_x_ref ) + ( m_y_out – m_y_ref ) + ( m_z_out – m_z_ref ) > M_VECM_THS value and t > M_VECM_CNT value. Where m_x_out, m_y_out, and m_z_out are the current decimated magnetometer output values, and m_x_ref, m_y_ref, and m_z_ref are the internally latched reference values.
10.18.2 M_VECM_THS_MSB (0x6A) register Table 206. M_VECM_THS_MSB register m_vecm_dbcntm m_vecm_ths[14:8] 0 0b000_0000 Table 207. M_VECM_THS_MSB bit descriptions Field Description m_vecm_dbcntm Magnetic vector-magnitude debounce counter mode selection: 0: The debounce counter is decremented by 1 whenever the current vector-magnitude result is below the threshold set in M_VECM_THS. 1: The debounce counter is cleared whenever the current vector-magnitude result is below the threshold set in M_VECM_THS.
10.18.5 M_VECM_INITX_MSB (0x6D) register Table 211. M_VECM_INITX_MSB register m_vecm_initx[15:8] 0b0000_0000 Table 212. M_VECM_INITX_MSB bit description Field m_vecm_initx[15:8] Description MSB of signed 16-bit initial X-axis value used by the magnetic vector-magnitude function when M_VECM_CFG[m_vecm_initm] = 1. 10.18.6 M_VECM_INITX_LSB (0x6E) register Table 213. M_VECM_INITX_LSB register m_vecm_initx[7:0] 0b0000_0000 Table 214.
10.18.9 M_VECM_INITZ_MSB (0x71) register Table 219. M_VECM_INITZ_MSB register m_vecm_initz[15:8] 0b0000_0000 Table 220. M_VECM_INITZ_MSB bit description Field m_vecm_initz[15:8] Description MSB of signed 16-bit initial Z-axis value used by the magnetic vector-magnitude function when M_VECM_CFG[m_vecm_initm] = 1. 10.18.10 M_VECM_INITZ_LSB (0x72) register Table 221. M_VECM_INITZ_LSB register m_vecm_initz[7:0] 0b0000_0000 Table 222.
11 Mounting Guidelines for the Quad Flat No-Lead (QFN) Package Printed Circuit Board (PCB) layout is a critical portion of the total design. The footprint for the surface mount packages must be the correct size to ensure proper solder connection interface between the PCB and the package. With the correct footprint, the packages will self-align when subjected to a solder reflow process. These guidelines are for soldering and mounting the Quad Flat No-Lead (QFN) package inertial sensors to PCBs.
PCB Land Pattern & Stencil Package Footprint 0.567 mmxx0.25mm 0.25 mm 0.467mm Package footprint Solder mask opening = PCB land pad edge + 0.113mm larger all around PCB land pad = 0.8mm x 0.3mm No copper in this area Stencil opening = PCB land pad -0.015mm smaller all around = 0.77mm x 0.27mm Figure 20. Recommended PCB land pattern, solder mask, and stencil opening near package footprint Figure 21. Detailed dimensions FXOS8700CQ Sensors Freescale Semiconductor, Inc.
12 Package Thermal Characteristics Table 223. Thermal resistance data Rating Description Junction-to-ambient, natural convection(1)(2) Single-layer board Junction-to-ambient, natural convection(1)(3) Four-layer board (two signals, two planes) Junction-to-board(4) Junction-to-case (top)(5) Junction-to-package (top) (6) Natural convection Symbol RθJA Value 163 Unit °C/W 70 RθJB 33 °C/W RθJCTop 84 °C/W ΨJT 6 °C/W 1.
13 Package CASE 2188-02 ISSUE A 16 LEAD QFN FXOS8700CQ Sensors Freescale Semiconductor, Inc.
CASE 2188-02 ISSUE A 16 LEAD QFN FXOS8700CQ 94 Sensors Freescale Semiconductor, Inc.
CASE 2188-02 ISSUE A 16 LEAD QFN FXOS8700CQ Sensors Freescale Semiconductor, Inc.
14 Revision History Table 224. Revision history Revision number Revision date 0.1 05/2012 • Corrected Figure 1 and updated Figure 4 to include acceleration values. 05/2012 • Added Autonomous sub-bullets to first page. • Table 2: Changed Cross-axis Max value to ±0.5 and Die-to-package alignment error Max value to ±2. • Table 13: WHO_AM_I register, Default Hex Value numbers changed from 0xC4/0xC7 to 0xC7 removed Note 4 and 5. • Section 9.1.
Table 224. Revision history (Continued) Revision number 2 Revision date Description of changes 05/2013 • Changed title of document. • Table 1: Added footnotes. • Table 2: Added footnotes. Updated Sensitivity change with temperature row Typ value from 0.008 to 0.01. Changed Zero-g level change versus temperature Typ value from ±0.15 to ±0.2. Changed Typ value in Hysteresis from ±1 to ±0.5. Updated Nonlinearity row from TBD to 0.25 %FSACCEL.
Table 224. Revision history (Continued) Revision number 3 Revision date Description of changes 07/2013 • Added new Section 3 Example Driver Code. • Table 5: Updated Test Conditions column for Nonlinearity from ±2 g to ±1 g. Added footnote 7 to Output noise density row. • Section 6.2.4: Added toggle information to end of paragraph. • Table 15: Updated Comment column for Register addresses 0x07-0x08, 0x1D, 0x51, and 0x79. Updated contents of NOTE following table. • Section 10.1.
Appendix A A.1 A.1.1 Errata SPI Mode Soft-reset using CTRL_REG2 (0x2B), bit 6 Description: Following a soft-reset command, issued by setting CTRL_REG2[rst] = 1, certain device-specific parameters do not get updated correctly from NVM, causing inaccurate data output and incorrect WHOAMI (0x0D) register content. This behavior happens only in SPI mode. In I2C mode the device works as advertised. Workaround: Avoid using soft-reset in SPI mode by alternately utilizing the hardware RESET pin.
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