Freescale Semiconductor, Inc. Data Sheet: Advance Information FXAS21000 Rev 1.2, 7/2014 Xtrinsic 3-Axis Digital Angular Rate Gyroscope FXAS21000 FXAS21000 is a small, low-power, 3-axis yaw, pitch, and roll angular rate gyroscope. The full-scale range is adjustable from ±200°/s to ±1600°/s, with Output Data Rates (ODR) from 1.5625 to 200 Hz. It features both I2C and SPI interfaces.
Ordering Information Part Number Temperature Range Package Description Shipping FXAS21000CQR1 –40 °C to +85 °C QFN Tape and reel (1 k) Related Documentation The FXAS21000 device features and operations are described in a variety of reference manuals, user guides, and application notes. To find the most-current versions of these documents: 1. Go to the Freescale homepage at freescale.com. 2. In the Keyword search box at the top of the page, enter the device number FXAS21000. 3.
Table of Contents 1 General Description......................................................................... 4 1.1 Block Diagram.......................................................................4 1.2 Pinout.....................................................................................4 1.3 System Connections.............................................................. 6 1.3.1 Typical Application Circuit—I2C Mode................. 6 1.3.2 Typical Application Circuit—SPI Mode..................
General Description 1 General Description 1.
General Description Reserved Reserved Reserved Reserved Reserved 1.2 Pinout 24 23 22 21 20 GND 1 19 GND INT2 2 18 VDDIO 17 SPI_CS_B 16 VREGD FXAS21000 4 mm x 4 mm x 1 mm 5 6 Reserved 7 8 9 10 11 15 VDD 14 GND 13 SA0 / MISO 12 SDA / MOSI / SPI_DIO GND Reserved SCL / SCLK 24 pin QFN Reserved 4 Reserved 3 Reserved INT1 RST_B Figure 2. Device pinout (top view) Table 1.
General Description Table 1. Pin functions (continued) Pin Name Function 22 Reserved Reserved - Must be tied to ground 23 Reserved Reserved - Must be tied to ground 24 Reserved Reserved - Must be tied to ground 1. MOSI becomes a bidirectional data pin when FXAS21000 is operated in 3-wire SPI mode with CTRL_REG0[SPIW] = 1. 1.3 System Connections The FXAS21000 offers the choice of connecting to a host processor through either I2C or SPI interfaces.
General Description VDDIO 47 kΩ (Optional) INT1 20 Reserved 2 21 Reserved INT2 22 Reserved GND 23 Reserved 1 24 Reserved 1.3.2 Typical Application Circuit—SPI Mode GND 19 INT2 VDDIO 18 3 INT1 SPI_CS_B 17 4 RST_B VREGD 16 5 GND VDD 15 6 Reserved GND 14 7 Reserved Host SPI Chip Select VDD (1.95 – 3.6 V) 1.0 μF Reserved Reserved SCLK MOSI/SPI_DIO 0.1 μF Reserved Note: Connect RST_B pin to VDDIO if unused in the application. A pull-up resistor may be used if desired.
Mechanical and Electrical Specifications 2 Mechanical and Electrical Specifications 2.1 Temperature Sensor Characteristics Table 2. Temperature sensor characteristics Characteristic Symbol Condition(s) Min Typ Max Unit Full scale range TFSR — –40 — +85 °C 25 °C — ±1 — Over Temperature Range — ±3 — Temperature Accuracy — Operating Temperature TOP — –40 +25 +85 °C TSENS — — 1 — °C/LSB Temperature sensor sensitivity °C Test conditions (unless otherwise noted): • VDD = 2.
Mechanical and Electrical Specifications Table 4. ESD and latch-up protection characteristics Rating Symbol Value Unit Human body model (HBM) VHBM ±2000 V Machine model (MM) VMM ±200 V Charge device model (CDM) VCDM ±500 V Latch-up current at T = 85 °C ILU ±100 mA Caution This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part. Caution This is an ESD sensitive device, improper handling can cause permanent damage to the part. 2.
Mechanical and Electrical Specifications 2.4 Mechanical Characteristics Table 6. Mechanical characteristics Parameter Symbol Test Conditions Min FS = 00 Full-scale range Sensitivity1 FS So Typ Max Unit — dps — dps/LSB ±1600 FS = 01 — FS = 10 ±800 ±400 FS = 11 ±200 FS = 00 0.2 FS = 01 — FS = 10 FS = 11 0.1 0.05 0.025 Sensitivity change vs. temperature TCS –40 °C ≤ T ≤ 85 °C — ±0.
Digital Interfaces 2.5 Electrical Characteristics Table 7. Electrical characteristics Parameter Symbol Test conditions Min Typ Max Unit Current consumption IddAct Active Mode; Probe data on a trimmed oscillator and iref — 5.8 — mA Supply current drain in Standby mode IddStby Standby mode — 2 — µA Supply current drain in Ready mode IddRdy Ready mode — 4.8 — mA High-level output voltage INT1, INT2 VOH IO = 500 µA 0.
Digital Interfaces Table 8. Serial interface pin descriptions Pin name VDDIO I2C/SPI_CS_B SCL/SCLK Pin description Digital interface power I2C/SPI interface mode selection and SPI chip select pin I2C/SPI serial clock SDA/MOSI/SPI_DIO I2C serial data/SPI master serial data out slave serial data in, SPI 3-wire data In/Out (in 3wire SPI mode with CTRL_REG0[SPIW]=1) SA0/MISO I2C least significant slave device address bit/SPI master serial data in slave serial data out 3.
Digital Interfaces 2. tHD;DAT is the data-hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge. 3. The maximum tHD;DAT could be 3.45 µs and 0.9 µs for Standard mode and Fast mode, but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time. 4. tVD;ACK = time for acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse). 5. tSU;DAT = maximum tf for the SDA and SCL bus lines is specified at 300 ns.
Digital Interfaces A transaction on the bus is started through a start condition (ST) signal, which is defined as a HIGH-to-LOW transition on the data line while the SCL line is held HIGH. After the ST signal has been transmitted by the master, the bus is considered busy. The next byte of data transmitted contains the slave address in the first seven bits, and the eighth bit, the read/write bit, indicates whether the master is receiving data from the slave or transmitting data to the slave.
Digital Interfaces previously selected register. The FXAS21000 then acknowledges and transmits the data from the requested register. The master does not transmit a no acknowledge (NACK), but transmits an SP to end the data transfer. 3.1.2.2 Multiple-Byte Read When performing a multiple-byte or burst read, the FXAS21000 increments the register address read pointer after a read command is received.
Digital Interfaces 3.1.3.
Digital Interfaces 3.2 General SPI Operation (4-Wire Mode) The SPI_CS_B pin is driven low at the start of a SPI transaction, held low for the duration of the transaction, and driven high after the transaction is complete. During a transaction, the master toggles the SPI clock (SCLK). The SCLK polarity is defined as having an idle value that is low and phase where data is captured on the clock's rising edge and propagated on the falling edge.
Digital Interfaces SPI_CS_B SCLK MOSI 1 2 R/W A6 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 MISO Figure 9. SPI multiple write operation showing 2 bytes written 3.2.2 SPI Single Read (4-Wire Mode) NOTE this description pertains only to the default SPI 4-wire interface mode (with CTRL_REG0[SPIW] = 0). This mode is the default out of POR, or after a hard/soft reset.
Digital Interfaces SPI_CS_B SCLK MOSI 2 3 R/W A6 A5 1 4 A4 5 6 7 8 A3 A2 A1 A0 MISO 9 D7 10 D6 11 D5 12 D4 13 D3 14 D2 15 D1 16 D0 17 D7 18 D6 19 D5 20 D4 21 D3 22 D2 23 D1 24 D0 Figure 11. SPI multiple read operation showing 2 bytes written 3.2.3 SPI 3-Wire Mode The FXAS21000 can be configured to operate in 3-wire mode. In this mode the only signal pins used are SPI_CS_B, SCLK, and SPI_DIO; the MISO pin is not used.
Modes of Operation 4 Modes of Operation The device may be placed into one of three functional modes: • Standby: Some digital blocks are enabled; I2C/SPI communication with FXAS21000 is possible. • Active: All blocks are enabled (digital and analog), the device is actively measuring the angular rate at the ODR specified in 0x13: CTRL_REG1. • Ready: The drive circuits are running, but no measurements are being made. The functional mode is selected using 0x13: CTRL_REG1.
Functionality • Configurable high-pass filter cutoff frequency; Integrated Anti-Aliasing Filter (AAF) limits output data bandwidth to ODR/2 • Embedded rate threshold detection with programmable debounce timer • 32-sample (X/Y/Z data at 14-bit) FIFO, configurable operating mode (Circular, Stop, Triggered) • 2 external interrupt pins that are configurable to trigger on data-ready, rate threshold, or FIFO events • Self-test function for indication of device health • Single control bit for zero-rate offset com
Functionality The FIFO can be configured to operate in Circular Buffer mode or Stop mode, depending on the settings made in the 0x09: F_SETUP register. The Circular Buffer mode allows the FIFO to be filled with a new sample replacing the oldest sample in the buffer. The most recent 32 samples will be stored in the buffer. This is useful in situations where the processor is waiting for a specific interrupt to indicate that the data must be flushed to analyze the event.
Functionality Output data rate (Hz) Counter clock period (ms) Event duration range 6.25 160 0 – 40.8 3.125 320 0 – 81 1.5625 640 0 – 163 The rate threshold (RT) event flag is set in the 0x0B: INT_SOURCE_FLAG register. It is cleared by reading the RT_SRC register. Using 0x14: CTRL_REG2, the device can be configured to generate an external interrupt on either the INT1 or INT2 pin when a rate threshold event condition occurs. Data RT_THS Counter control Counter value RT_COUNT RT t Figure 14.
Register Descriptions Data RT_THS Counter control Counter value RT_COUNT RT Resetting the flag t Figure 17. RT example 4 6 Register Descriptions Table 12.
Register Descriptions 6.1 0x00: STATUS The STATUS register content depends on the FIFO mode setting. It is a copy of either 0x07: DR_STATUS or 0x08: F_STATUS. This allows for easy reading of the relevant status register before reading the current sample output data, or the first sample stored in the FIFO. 6.2 0x01–0x06: OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, OUT_Z_LSB X-, Y-, and Z-axis sample data are represented in 14-bit, 2's complement format.
Register Descriptions NOTE After OUT_Z_LSB is read, the next read register by the autoincrement process is STATUS at 0x00. Table 13. OUT_X_MSB register (default value 0x00) Bit 7 6 5 4 Read 3 2 1 0 0 0 0 0 1 0 0 0 0 0 XD[13:6] Write Reset 0 0 0 0 Table 14. OUT_X_LSB register (default value 0x00) Bit 7 6 5 Read 4 3 2 XD[5:0] Write Reset 0 0 0 0 0 0 Table 15.
Register Descriptions Table 18. OUT_Z_LSB register (default value 0x00) Bit 7 6 5 Read 4 3 2 ZD[5:0] 1 0 0 0 0 0 Write Reset 0 0 0 0 0 0 6.3 0x07: DR_STATUS The DR_STATUS register provides the sample data acquisition status and reflects the real-time updates to the OUT_X, OUT_Y, and OUT_Z registers. The content of this register is reset upon a transition from Standby to Active or from Ready to Active modes. Table 19.
Register Descriptions Table 20. DR_STATUS field descriptions (continued) Field 5 YOW Description Y-axis data overwrite • Asserted whenever a new Y-axis acquisition is completed before the retrieval of the previous data. When this occurs, the previous data is overwritten. • Cleared anytime the OUT_Z_MSB (and respectively OUT_Y_MSB, OUT_X_MSB) register is read.
Register Descriptions 6.4 0x08: F_STATUS Indicates the current status of the FIFO, when the FIFO is enabled. When the FIFO is enabled, the STATUS register (address 0x00) also contains the same content as this register to facilitate the emptying of the FIFO by the host processor. The content of this register is reset upon a transition from Standby to Active or from Ready to Active modes. The SRC_FIFO bit in the 0x0B: INT_SOURCE_FLAG register is cleared when F_STATUS is read. Table 21.
Register Descriptions Table 23. F_Setup register Bit Read Write Reset 7 6 5 4 F_MODE[1:0] 0 3 2 1 0 0 0 F_WMRK[5:0] 0 0 0 0 0 Table 24. F_SETUP field descriptions Field 7:6 F_MODE Description Selects the FIFO operating mode • In the Circular Buffer mode, the oldest sample is discarded and replaced by the newest sample when the buffer is full (F_STATUS[F_CNT] = 32). • In the Stop mode, the FIFO will stop accepting new samples when the buffer is full ( F_STATUS[F_CNT] = 32).
Register Descriptions 6.6 0x0A: F_EVENT The F_EVENT register is used to monitor the system state and FIFO event status. The content of this register is reset upon a transition from Standby to Active or from Ready to Active modes. Table 25. F_Event register Bit 7 6 5 Read 0 0 F_EVENT 0 0 0 4 3 2 1 0 0 0 FE_TIME[4:0] Write Reset 0 0 0 Table 26. F_EVENT field descriptions Field 5 F_EVENT Description FIFO Event • Indicates if either F_WMKF or F_OVF flags are set (logical OR).
Register Descriptions Table 28. INT_SRC_FLAG field descriptions Field 3 BOOTEND Description Boot sequence complete event flag • Asserted as soon as the device boot sequence has completed.
Register Descriptions Table 30. CTRL_REG0 Bit Read Write Reset 7 6 5 4 0 0 SPIW 0 0 0 3 SEL[1:0] 0 2 1 HPF_EN 0 0 0 FS[1:0] 0 0 Table 31.
Register Descriptions Table 33. Selectable Full Scale Ranges (continued) FS1 FS0 Range (dps) Nominal Sensitivity (dps/LSB) 1 0 ±400 0.05 1 1 ±200 0.025 6.10 0x0E: RT_CFG The RT_CFG register is used to enable the Rate Threshold interrupt generation. Table 34. RT_ CFG Register Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 ELE ZTEFE YTEFE XTEFE 0 0 0 0 0 0 0 0 Table 35.
Register Descriptions 6.11 0x0F: RT_SRC This register indicates the source of the Rate Threshold event. It also clears the RT_SRC flag in the 0x0B: INT_SOURCE_FLAG register. Table 36. RT_ SRC Register Bit 7 6 5 4 3 2 1 0 Read 0 EA ZRT Z_RT_Pol YRT Y_RT_Pol XRT X_RT_Pol 0 0 0 0 0 0 0 0 Write Reset Table 37. RT_SRC field descriptions Field 6 EA Description Event active flag • Asserted whenever a rate threshold event has been detected on one or more of the enabled axes.
Register Descriptions Table 37. RT_SRC field descriptions (continued) Field 2 Y_RT_Pol Description Polarity of Y event • Indicates the rate polarity for the event detected on the Y axis 0: Y rate event was Positive 1: Y rate event was Negative 1 XRT X rate Event • Indicates that a rate threshold event (as defined in Modes of Operation) has been detected on the X axis • Cleared when read if it has been latched (ELE = 1).
Register Descriptions Table 39. RT_THS field descriptions (continued) Field 6:0 THS Description Unsigned 7-bit rate threshold value • The contents should only be modified when the device is in Standby mode • The internal state of the Rate Threshold function is reset when a transition from Standby to Active or Ready to Active modes occurs. • The rate threshold in dps is given by the following formula: 6.13 0x11: RT_COUNT RT_COUNT sets the number of debounce counts.
Register Descriptions Table 42. TEMP register Bit 7 6 5 4 Read 3 2 1 0 0 0 0 0 Temp[7:0] Write Reset 0 0 0 0 6.15 0x13: CTRL_REG1 The CTRL_REG1 register is used to configure the device ODR, set the operating mode, and exercise the self-test and zero-rate offset adjustment functions. NOTE Control bits in CTRL_REG1 should be changed only in Standby or Ready mode. Accuracy of the data is not guaranteed if these bits are changed when the device is in Active mode. Table 43.
Register Descriptions Table 44. CTRL_REG1 field descriptions (continued) Field Description Self-test enable • Activates the self-test function. • When ST is set, a data output change will occur even if no angular rate is applied. This allows the host application to check the functionality of the sensor and the entire measurement signal chain.
Register Descriptions Table 46. Device mode Active Ready Device mode 0 0 Standby 0 1 Ready 1 x Active 6.16 0x14: CTRL_REG2 This register enables and assigns the output pin(s) and logic polarities for the various interrupt sources available on the device. Table 47. CTRL_REG2 register Bit 7 Read Write 6 5 4 3 2 1 0 INT_CFG_FIFO INT_EN_FIFO INT_CFG_RT INT_EN _RT INT_CFG_DRDY INT_EN_DRDY IPOL PP_OD Reset 0 0 0 0 0 0 0 0 Table 48.
Register Descriptions Table 48. Interrupt Enable register descriptions (continued) Register 2 INT_EN_DRDY 1 IPOL 0 PP_OD Description Data ready interrupt enable 0: Data-ready interrupt disabled 1: Data-ready interrupt enabled Interrupt logic polarity 0: Active low 1: Active high INT1 and INT2 pin output driver configuration 0: Push-pull output driver 1: Open-drain output driver Table 49.
Printed Circuit Board Layout and Device Mounting 7 Printed Circuit Board Layout and Device Mounting Printed Circuit Board (PCB) layout and device mounting are critical to the overall performance of the design. The footprint for the surface mount packages must be the correct size as a base for a proper solder connection between the PCB and the package. This, along with the recommended soldering materials and techniques, will optimize assembly and minimize the stress on the package after board mounting.
Printed Circuit Board Layout and Device Mounting 4X 2.175 4 8 24X 0.30 0.18 12 7 24X 0.8 24X 0.3 13 24X 0.725 0.525 20X 0.5 4 1 19 24 20 20X 0.5 Package outline Package PCB land pad 4.576 4X 2.160 Package outline 4X 1.438 24X 0.769 24X 0.269 4X 1.938 20X 0.5 4.576 Package outline Solder stencil opening Solder mask opening Figure 18. Footprint 7.2 Overview of Soldering Considerations The information provided here is based on experiments executed on QFN devices.
Package Information • Use a standard pick-and-place process and equipment. Do not use a hand soldering process. • Do not use a screw-down or stacking to mount the PCB into an enclosure. These methods could bend the PCB, which would put stress on the package. 7.3 Halogen Content This package is designed to be Halogen Free, exceeding most industry and customer standards. Halogen Free means that no homogeneous material within the assembled package will contain chlorine (Cl) in excess of 700 ppm or 0.
Package Information 8.2 Tape and Reel Information Figure 19. Tape dimensions Pin 1 Direction to unreel Barcode label side of reel Figure 20. Tape and reel orientation Xtrinsic 3-Axis Digital Angular Rate Gyroscope, Rev1.2, 7/2014. 45 Freescale Semiconductor, Inc.
Package Information 8.3 Package Description This drawing is located at freescale.com. 46 Freescale Semiconductor, Inc. Xtrinsic 3-Axis Digital Angular Rate Gyroscope, Rev1.2, 7/2014.
Revision History 9 Revision History Revision number Revision date 1.0 09/2013 Initial release of document 1.1 10/2013 Register address map, Comments column, 5:0 was 7:2 (3 plcs) Description RT_THS register table, THS[6:0] was THS[6:3] Electrical Characteristics, IddRdy, Typ, 4.8 was 3.8 1.2 7/2014 Figures 3 and 4, changed value of capacitor on pins 18/19 and 14/15 from 1.0 to 0.1 and added a 0.
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