Datasheet
UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 108 of 547
NXP Semiconductors
UM10398
Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)
Some input functions (SCK0, DSR, DCD, RI, SSEL1, CT16B0_CAP0, SCK1, MISO1,
MOSI1, CT32B0_CAP0, and RXD) are multiplexed to several physical pins. The
IOCON_LOC registers select the pin location for each of these functions.
Remark: The IOCON registers are listed in order of their memory locations in Table 104
,
which correspond to the order of their physical pin numbers in the LQFP48 package
starting at the upper left corner with pin 1 (PIO2_6). See Table 105
for a listing of IOCON
registers ordered by port number.
The IOCON location registers are used to select a physical pin for multiplexed functions.
Remark: Note that once the pin location has been selected, the function still must be
configured in the corresponding IOCON registers for the function to be usable on that pin.
Table 104. Register overview: I/O configuration (base address 0x4004 4000)
Name Access Address
offset
Description Reset
value
Reference
IOCON_PIO2_6 R/W 0x000 I/O configuration for pin PIO2_6/
CT32B0_MAT1
0xD0 Ta ble 106
- R/W 0x004 Reserved - -
IOCON_PIO2_0 R/W 0x008 I/O configuration for pin
PIO2_0/DTR
/SSEL1
0xD0 Ta ble 107
IOCON_RESET_PIO0_0 R/W 0x00C I/O configuration for pin RESET/PIO0_0 0xD0 Table 108
IOCON_PIO0_1 R/W 0x010 I/O configuration for pin
PIO0_1/CLKOUT/CT32B0_MAT2
0xD0 Ta ble 106
IOCON_PIO1_8 R/W 0x014 I/O configuration for pin
PIO1_8/CT16B1_CAP0
0xD0 Ta ble 110
IOCON_SSEL1_LOC R/W 0x018 SSEL1 pin location select register 0x0 Table 152
IOCON_PIO0_2 R/W 0x01C I/O configuration for pin
PIO0_2/SSEL0/CT16B0_CAP0
0xD0 Table 111
IOCON_PIO2_7 R/W 0x020 I/O configuration for pin PIO2_7/
CT32B0_MAT2/RXD
0xD0 Ta ble 112
IOCON_PIO2_8 R/W 0x024 I/O configuration for pin PIO2_8/
CT32B0_MAT3/TXD
0xD0 Ta ble 113
IOCON_PIO2_1 R/W 0x028 I/O configuration for pin
PIO2_1/DSR/SCK1
0xD0 Ta ble 114
IOCON_PIO0_3 R/W 0x02C I/O configuration for pin PIO0_3 0xD0 Table 115
IOCON_PIO0_4 R/W 0x030 I/O configuration for pin PIO0_4/SCL 0x00 Table 116
IOCON_PIO0_5 R/W 0x034 I/O configuration for pin PIO0_5/SDA 0x00 Table 117
IOCON_PIO1_9 R/W 0x038 I/O configuration for pin
PIO1_9/CT16B1_MAT0/ MOSI1
0xD0 Ta ble 118
IOCON_PIO3_4 R/W 0x03C I/O configuration for pin PIO3_4/
CT16B0_CAP1/RXD
0xD0 Ta ble 119
IOCON_PIO2_4 R/W 0x040 I/O configuration for pin PIO2_4/
CT16B1_MAT1/ SSEL1
0xD0 Ta ble 120
IOCON_PIO2_5 R/W 0x044 I/O configuration for pin PIO2_5/
CT32B0_MAT0
0xD0 Ta ble 121
IOCON_PIO3_5 R/W 0x048 I/O configuration for pin PIO3_5/
CT16B1_CAP1/TXD
0xD0 Ta ble 122
IOCON_PIO0_6 R/W 0x04C I/O configuration for pin PIO0_6/SCK0 0xD0 Ta ble 123