Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 109 of 547
NXP Semiconductors
UM10398
Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)
IOCON_PIO0_7 R/W 0x050 I/O configuration for pin PIO0_7/CTS 0xD0 Table 12 4
IOCON_PIO2_9 R/W 0x054 I/O configuration for pin PIO2_9/
CT32B0_CAP0
0xD0 Ta ble 125
IOCON_PIO2_10 R/W 0x058 I/O configuration for pin PIO2_10 0xD0 Table 126
IOCON_PIO2_2 R/W 0x05C I/O configuration for pin
PIO2_2/DCD/MISO1
0xD0 Ta ble 127
IOCON_PIO0_8 R/W 0x060 I/O configuration for pin
PIO0_8/MISO0/CT16B0_MAT0
0xD0 Ta ble 128
IOCON_PIO0_9 R/W 0x064 I/O configuration for pin
PIO0_9/MOSI0/CT16B0_MAT1
0xD0 Ta ble 129
IOCON_SWCLK_PIO0_10 R/W 0x068 I/O configuration for pin
SWCLK/PIO0_10/
SCK0/CT16B0_MAT2
0xD0 Ta ble 130
IOCON_PIO1_10 R/W 0x06C I/O configuration for pin
PIO1_10/AD6/CT16B1_MAT1/ MISO1
0xD0 Ta ble 131
IOCON_PIO2_11 R/W 0x070 I/O configuration for pin PIO2_11/SCK0/
CT32B0_CAP1
0xD0 Ta ble 132
IOCON_R_PIO0_11 R/W 0x074 I/O configuration for pin
R/PIO0_11/AD0/CT32B0_MAT3
0xD0 Ta ble 133
IOCON_R_PIO1_0 R/W 0x078 I/O configuration for pin
R/PIO1_0/AD1/CT32B1_CAP0
0xD0 Ta ble 134
IOCON_R_PIO1_1 R/W 0x07C I/O configuration for pin
R/PIO1_1/AD2/CT32B1_MAT0
0xD0 Ta ble 135
IOCON_R_PIO1_2 R/W 0x080 I/O configuration for pin
R/PIO1_2/AD3/CT32B1_MAT1
0xD0 Ta ble 136
IOCON_PIO3_0 R/W 0x084 I/O configuration for pin
PIO3_0/DTR
/CT16B0_MAT0/TXD
0xD0 Ta ble 137
IOCON_PIO3_1 R/W 0x088 I/O configuration for pin
PIO3_1/DSR
/CT16B0_MAT1/RXD
0xD0 Ta ble 138
IOCON_PIO2_3 R/W 0x08C I/O configuration for pin
PIO2_3/RI/MOSI1
0xD0 Ta ble 139
IOCON_SWDIO_PIO1_3 R/W 0x090 I/O configuration for pin
SWDIO/PIO1_3/AD4/CT32B1_MAT2
0xD0 Ta ble 140
IOCON_PIO1_4 R/W 0x094 I/O configuration for pin
PIO1_4/AD5/CT32B1_MAT3
0xD0 Ta ble 141
IOCON_PIO1_11 R/W 0x098 I/O configuration for pin
PIO1_11/AD7/CT32B1_CAP1
0xD0 Ta ble 142
IOCON_PIO3_2 R/W 0x09C I/O configuration for pin PIO3_2/DCD/
CT16B0_MAT2/SCK1
0xD0 Ta ble 143
IOCON_PIO1_5 R/W 0x0A0 I/O configuration for pin
PIO1_5/RTS
/CT32B0_CAP0
0xD0 Ta ble 144
IOCON_PIO1_6 R/W 0x0A4 I/O configuration for pin
PIO1_6/RXD/CT32B0_MAT0
0xD0 Ta ble 145
IOCON_PIO1_7 R/W 0x0A8 I/O configuration for pin
PIO1_7/TXD/CT32B0_MAT1
0xD0 Ta ble 146
Table 104. Register overview: I/O configuration (base address 0x4004 4000)
Name Access Address
offset
Description Reset
value
Reference