Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 140 of 547
NXP Semiconductors
UM10398
Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)
8.4.50 IOCON_MISO1_LOC
8.4.51 IOCON_MOSI1_LOC
8.4.52 IOCON_CT32B0_CAP0_LOC
Table 155. IOCON MISO1 location register (IOCON_MISO1_LOC, address 0x4004 40C8) bit
description
Bit Symbol Value Description Reset
value
1:0 MISO1LOC Selects pin location for the MISO1 function. 00
0x0 Selects MISO1 function in pin location
PIO2_2/DCD
/MISO1 (see Table 127).
0x1 Selects MISO1 function in pin location
PIO1_10/AD6/CT16B1_MAT1/MISO1 (see Table 131
).
0x2 Reserved.
0x3 Reserved.
31:2 - - Reserved. -
Table 156. IOCON MOSI1 location register (IOCON_MOSI1_LOC, address 0x4004 40CC) bit
description
Bit Symbol Value Description Reset
value
1:0 MOSI1LOC Selects pin location for the MOSI1 function. 00
0x0 Selects MOSI1 function in pin location PIO2_3/RI
/MOSI1
(see Table 139
).
0x1 Selects MOSI1 function in pin location
PIO1_9/CT16B1_MAT0/MOSI1 (see Table 118
).
0x2 Reserved.
0x3 Reserved.
31:2 - - Reserved. -
Table 157. IOCON CT32B0_CAP0 location register (IOCON_CT32B0_CAP0_LOC, address
0x4004 40D0) bit description
Bit Symbol Value Description Reset
value
1:0 CT32B0_CAP0LOC Selects pin location for the CT32B0_CAP0
function.
00
0x0 Selects CT32B0_CAP0 function in pin location
PIO1_5/RTS
/CT32B0_CAP0 (see Table 144).
0x1 Selects CT32B0_CAP0 function in pin location
PIO2_9/CT32B0_CAP0 (Table 125
).
0x2 Reserved.
0x3 Reserved.
31:2 - - Reserved. -