Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 144 of 547
NXP Semiconductors
UM10398
Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,
Fig 17. Pin configuration HVQFN33 package
002aae698
Transparent top view
PIO0_8/MISO0/CT16B0_MAT0
PIO1_8/CT16B1_CAP0
PIO0_2/SSEL0/CT16B0_CAP0
PIO0_9/MOSI0/CT16B0_MAT1
V
DD
SWCLK/PIO0_10/SCK0/CT16B0_MAT2
XTALOUT PIO1_10/AD6/CT16B1_MAT1
XTALIN R/PIO0_11/AD0/CT32B0_MAT3
PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO1_0/AD1/CT32B1_CAP0
RESET/PIO0_0 R/PIO1_1/AD2/CT32B1_MAT0
PIO2_0/DTR R/PIO1_2/AD3/CT32B1_MAT1
PIO0_3
PIO0_4/SCL
PIO0_5/SDA
PIO1_9/CT16B1_MAT0
PIO3_4 PIO3_5
PIO0_6/SCK0
PIO0_7/CTS
PIO1_7/TXD/CT32B0_MAT1 PIO1_6/RXD/CT32B0_MAT0 PIO1_5/RTS/CT32B0_CAP0 V
DD
PIO3_2 PIO1_11/AD7 PIO1_4/AD5/CT32B1_MAT3/WAKEUP SWDIO/PIO1_3/AD4/CT32B1_MAT2
8 17
7 18
6 19
5 20
4 21
3 22
2 23
1 24
9
10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
terminal 1
index area
33 V
SS
Fig 18. Pin configuration HVQFN24 package
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LPC1112FHN24
Transparent top view
PIO0_9
V
DD
PIO1_8
PIO0_10
XTALIN PIO0_11
V
SS
PIO1_0
PIO0_1 PIO1_1
RESET/PIO0_0 PIO1_2
PIO0_2 PIO0_4 PIO0_5 PIO0_6 PIO0_7 PIO0_8
PIO1_7 PIO1_6 V
DD
V
SS
PIO1_4 PIO1_3
terminal 1
index area
6
13
5
14
4 15
3 16
2 17
1
18
7 8 9
10 11 12
24 23 22 21 20 19