Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 148 of 547
NXP Semiconductors
UM10398
Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,
9.5 LPC111x/LPC11Cxx Pin description
Table 160. LPC1113/14 and LPC11C12/C14 pin description table (LQFP48 package)
Symbol Pin Type Description
PIO0_0 to PIO0_11 I/O Port 0 — Port 0 is a 12-bit I/O port with individual direction and function
controls for each bit. The operation of port 0 pins depends on the function
selected through the IOCONFIG register block.
RESET/PIO0_0 3
[1][2]
I RESET — External reset input: A LOW on this pin resets the device,
causing I/O ports and peripherals to take on their default states, and
processor execution to begin at address 0.
In deep power-down mode, this pin must be pulled HIGH externally. The
RESET
pin can be left unconnected or be used as a GPIO pin if an external
RESET function is not needed.
I/O PIO0_0 — General purpose digital input/output pin.
PIO0_1/CLKOUT/
CT32B0_MAT2
4
[3][2]
I/O PIO0_1 — General purpose digital input/output pin. A LOW level on this pin
during reset starts the flash ISP command handler via UART (if PIO0_3 is
HIGH) or via C_CAN (if PIO0_3 is LOW).
O CLKOUT — Clockout pin.
O CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0
10
[3][2]
I/O PIO0_2 — General purpose digital input/output pin.
O SSEL0 — Slave Select for SPI0.
I CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 14
[3][2]
I/O PIO0_3 — General purpose digital input/output pin. This pin is monitored
during reset: Together with a LOW level on pin PIO0_1, a LOW level starts
the flash ISP command handler via C_CAN and a HIGH level starts the
flash ISP command handler via UART.
PIO0_4/SCL 15
[4][2]
I/O PIO0_4 — General purpose digital input/output pin (open-drain).
I/O SCL — I
2
C-bus, open-drain clock input/output. High-current sink only if I
2
C
Fast-mode Plus is selected in the I/O configuration register.
PIO0_5/SDA 16
[4][2]
I/O PIO0_5 — General purpose digital input/output pin (open-drain).
I/O SDA — I
2
C-bus, open-drain data input/output. High-current sink only if I
2
C
Fast-mode Plus is selected in the I/O configuration register.
PIO0_6/SCK0 22
[3][2]
I/O PIO0_6 — General purpose digital input/output pin.
I/O SCK0 — Serial clock for SPI0.
PIO0_7/CTS
23
[3][2]
I/O PIO0_7 — General purpose digital input/output pin (high-current output
driver).
I CTS
— Clear To Send input for UART.
PIO0_8/MISO0/
CT16B0_MAT0
27
[3][2]
I/O PIO0_8 — General purpose digital input/output pin.
I/O MISO0 — Master In Slave Out for SPI0.
O CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9/MOSI0/
CT16B0_MAT1
28
[3][2]
I/O PIO0_9 — General purpose digital input/output pin.
I/O MOSI0 — Master Out Slave In for SPI0.
O CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
SWCLK/PIO0_10/
SCK0/CT16B0_MAT2
29
[3][2]
I SWCLK — Serial wire clock.
I/O PIO0_10 — General purpose digital input/output pin.
I/O SCK0 — Serial clock for SPI0.
O CT16B0_MAT2 — Match output 2 for 16-bit timer 0.