Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 157 of 547
NXP Semiconductors
UM10398
Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V
DD
level); IA = inactive,
no pull-up/down enabled.
[2] RESET
functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep
power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.
[3] Pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
[4] I
2
C-bus pads compliant with the I
2
C-bus specification for I
2
C standard mode and I
2
C Fast-mode Plus. The pin requires an external
pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain
configuration applies to all functions on this pin.
[5] Pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When
configured as a ADC input, digital section of the pad is disabled.
[6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
XTALIN 4
[7]
- I - Input to the oscillator circuit and internal clock generator
circuits. Input voltage must not exceed 1.8 V.
V
DD
5; 22 - I - 3.3 V supply voltage to the internal regulator, the external rail,
and the ADC. Also used as the ADC reference voltage.
V
SS
3; 21 - I - Ground.
Table 162. LPC1112FHN24 Pin description table (HVQFN24 package)
Symbol HVQFN
pin
Start
logic
input
Type Reset
state
[1]
Description
Table 163. LPC11C24/C22 pin description table (LQFP48 package)
Symbol Pin Type Description
PIO0_0 to PIO0_11 Port 0 — Port 0 is a 12-bit I/O port with individual direction and function controls for
each bit. The operation of port 0 pins depends on the function selected through the
IOCONFIG register block.
RESET
/PIO0_0 3
[1]
I RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as
50 ns on this pin resets the device, causing I/O ports and peripherals to take on their
default states, and processor execution to begin at address 0.
In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin
can be left unconnected or be used as a GPIO pin if an external RESET
function is not
needed.
I/O PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter.
PIO0_1/CLKOUT/
CT32B0_MAT2
4
[3]
I/O PIO0_1 — General purpose digital input/output pin. A LOW level on this pin during
reset starts the flash ISP command handler via UART (if PIO0_3 is HIGH) or via
C_CAN (if PIO0_3 is LOW).
O CLKOUT — Clockout pin.
O CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0
10
[3]
I/O PIO0_2 — General purpose digital input/output pin.
I/O SSEL0 — Slave Select for SPI0.
I CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 14
[3]
I/O PIO0_3 — General purpose digital input/output pin. This pin is monitored during reset:
Together with a LOW level on pin PIO0_1, a LOW level starts the flash ISP command
handler via C_CAN and a HIGH level starts the flash ISP command handler via UART.
PIO0_4/SCL 15
[4]
I/O PIO0_4 — General purpose digital input/output pin (open-drain).
I/O SCL — I
2
C-bus, open-drain clock input/output. High-current sink only if I
2
C Fast-mode
Plus is selected in the I/O configuration register.