Datasheet
UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 165 of 547
NXP Semiconductors
UM10398
Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V
DD
level (V
DD
= 3.3 V));
IA = inactive, no pull-up/down enabled.
[2] RESET
functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep
power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
[4] I
2
C-bus pads compliant with the I
2
C-bus specification for I
2
C standard mode and I
2
C Fast-mode Plus. The pin requires an external
pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain
configuration applies to all functions on this pin.
S20 66 - O V
LCD
[7]
LCD segment output.
S21 67 - O V
LCD
[7]
LCD segment output.
S22 68 - O V
LCD
[7]
LCD segment output.
S23 69 - O V
LCD
[7]
LCD segment output.
S24 70 - O V
LCD
[7]
LCD segment output.
S25 71 - O V
LCD
[7]
LCD segment output.
S26 72 - O V
LCD
[7]
LCD segment output.
S27 73 - O V
LCD
[7]
LCD segment output.
S28 74 - O V
LCD
[7]
LCD segment output.
S29 75 - O V
LCD
[7]
LCD segment output.
S30 76 - O V
LCD
[7]
LCD segment output.
S31 77 - O V
LCD
[7]
LCD segment output.
S32 78 - O V
LCD
[7]
LCD segment output.
S33 79 - O V
LCD
[7]
LCD segment output.
S34 29 - O V
LCD
[7]
LCD segment output.
S35 30 - O V
LCD
[7]
LCD segment output.
S36 31 - O V
LCD
[7]
LCD segment output.
S37 32 - O V
LCD
[7]
LCD segment output.
S38 33 - O V
LCD
[7]
LCD segment output.
S39 34 - O V
LCD
[7]
LCD segment output.
BP0 42 - O V
LCD
[7]
LCD backplane output.
BP1 44 - O V
LCD
[7]
LCD backplane output.
BP2 43 - O V
LCD
[7]
LCD backplane output.
BP3 45 - O V
LCD
[7]
LCD backplane output.
LCD_SDA 35 - I/O
[7]
I
2
C-bus serial data input/output.
LCD_SCL 36 - I/O
[7]
I
2
C-bus serial clock input.
SYNC 37 - I/O
[7]
Cascade synchronization input/output.
CLK 38 - I/O
[7]
External clock input/output.
V
DD(LCD)
39 - - - 1.8 V to 5.5 V power supply: Power supply voltage for the
PCF8576D.
V
SS(LCD)
40 - - - LCD ground.
V
LCD
41 - - - LCD power supply; LCD voltage.
n.c. 3 - - - Not connected.
Table 164. LPC11D14 pin description table (LQFP100 package) …continued
Symbol Pin Start
logic
input
Type Reset
state
[1]
Description