Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 19 of 547
2.1 How to read this chapter
Table 4 and Table 5 show the memory configurations for different LPC111x/LPC11Cxx
parts.
2.2 Memory map
Figure 6 and Figure 7 show the memory and peripheral address space of the
LPC111x/LPC11Cxx.
The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.
On the LPC111x/LPC11Cxx, the GPIO ports are the only AHB peripherals. The APB
peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals. Each
peripheral of either type is allocated 16 kB of space. This allows simplifying the address
decoding for each peripheral.
All peripheral register addresses are 32-bit word aligned regardless of their size. An
implication of this is that word and half-word registers must be accessed all at once. For
example, it is not possible to read or write the upper byte of a word register separately.
UM10398
Chapter 2: LPC111x/LPC11Cxx Memory mapping
Rev. 12.3 — 10 June 2014 User manual
Table 4. LPC111x memory configuration
Part Flash SRAM
Suffix /101; /102; /103 /201; /202; /203 /301; /302;
/303; /323; /333
LPC1111 8 kB 2 kB 4 KB -
LPC1112 16 kB 2 kB 4 KB -
LPC1113 24 kB - 4 KB 8 kB
LPC1114/LPC11D14 32 kB - 4 KB 8 kB
LPC1114/323 48 kB - - 8 kB
LPC1114/333 56 kB - - 8 kB
LPC1115 64 kB - - 8 kB
Table 5. LPC11Cxx memory configuration
Part Flash SRAM
LPC11C12/301 16 kB 8 kB
LPC11C14/301 32 kB 8 kB
LPC11C22/301 16 kB 8 kB
LPC11C24/301 32 kB 8 kB