Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 191 of 547
NXP Semiconductors
UM10398
Chapter 12: LPC111x/LPC11Cxx General Purpose I/O (GPIO)
• All GPIO pins are inputs by default.
• Reading and writing of data registers are masked by address bits 13:2.
12.3 Register description
Each GPIO register can be up to 12 bits wide and can be read or written using word or
half-word operations at word addresses.
12.3.1 GPIO data register
The GPIOnDATA register holds the current logic state of the pin (HIGH or LOW),
independently of whether the pin is configured as an GPIO input or output or as another
digital function. If the pin is configured as GPIO output, the current value of the
GPIOnDATA register is driven to the pin.
A read of the GPIOnDATA register always returns the current logic level (state) of the pin
independently of its configuration. Because there is a single data register for both the
value of the output driver and the state of the pin’s input, write operations have different
effects depending on the pin’s configuration:
Table 173. Register overview: GPIO (base address port 0: 0x5000 0000; port 1: 0x5001 0000, port 2: 0x5002 0000;
port 3: 0x5003 0000)
Name Access Address offset Description Reset
value
GPIOnDATA R/W 0x0000 to 0x3FF8 Port n data address masking register
locations for pins PIOn_0 to PIOn_11 (see
Section 12.4.1
).
n/a
GPIOnDATA R/W 0x3FFC Port n data register for pins PIOn_0 to
PIOn_11
n/a
- - 0x4000 to 0x7FFC reserved -
GPIOnDIR R/W 0x8000 Data direction register for port n 0x00
GPIOnIS R/W 0x8004 Interrupt sense register for port n 0x00
GPIOnIBE R/W 0x8008 Interrupt both edges register for port n 0x00
GPIOnIEV R/W 0x800C Interrupt event register for port n 0x00
GPIOnIE R/W 0x8010 Interrupt mask register for port n 0x00
GPIOnRIS R 0x8014 Raw interrupt status register for port n 0x00
GPIOnMIS R 0x8018 Masked interrupt status register for port n 0x00
GPIOnIC W 0x801C Interrupt clear register for port n 0x00
- - 0x8020 - 0xFFFF reserved 0x00
Table 174. GPIOnDATA register (GPIO0DATA, address 0x5000 0000 to 0x5000 3FFC;
GPIO1DATA, address 0x5001 0000 to 0x5001 3FFC; GPIO2DATA, address 0x5002
0000 to 0x5002 3FFC; GPIO3DATA, address 0x5003 0000 to 0x5003 3FFC) bit
description
Bit Symbol Description Reset
value
Access
11:0 DATA Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW =
0.
n/a R/W
31:12 - Reserved - -