Datasheet
UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 193 of 547
NXP Semiconductors
UM10398
Chapter 12: LPC111x/LPC11Cxx General Purpose I/O (GPIO)
12.3.4 GPIO interrupt both edges sense register
12.3.5 GPIO interrupt event register
12.3.6 GPIO interrupt mask register
Bits set to HIGH in the GPIOnIE register allow the corresponding pins to trigger their
individual interrupts and the combined GPIOnINTR line. Clearing a bit disables interrupt
triggering on that pin.
12.3.7 GPIO raw interrupt status register
Bits read HIGH in the GPIOnRIS register reflect the raw (prior to masking) interrupt status
of the corresponding pins indicating that all the requirements have been met before they
are allowed to trigger the GPIOIE. Bits read as zero indicate that the corresponding input
pins have not initiated an interrupt. The register is read-only.
Table 177. GPIOnIBE register (GPIO0IBE, address 0x5000 8008 to GPIO3IBE, address 0x5003
8008) bit description
Bit Symbol Description Reset
value
Access
11:0 IBE Selects interrupt on pin x to be triggered on both edges (x = 0
to 11).
0 = Interrupt on pin PIOn_x is controlled through register
GPIOnIEV.
1 = Both edges on pin PIOn_x trigger an interrupt.
0x00 R/W
31:12 - Reserved - -
Table 178. GPIOnIEV register (GPIO0IEV, address 0x5000 800C to GPIO3IEV, address 0x5003
800C) bit description
Bit Symbol Description Reset
value
Access
11:0 IEV Selects interrupt on pin x to be triggered rising or falling
edges (x = 0 to 11).
0 = Depending on setting in register GPIOnIS (see
Table 176
), falling edges or LOW level on pin PIOn_x
trigger an interrupt.
1 = Depending on setting in register GPIOnIS (see
Table 176
), rising edges or HIGH level on pin PIOn_x
trigger an interrupt.
0x00 R/W
31:12 - Reserved - -
Table 179. GPIOnIE register (GPIO0IE, address 0x5000 8010 to GPIO3IE, address 0x5003
8010) bit description
Bit Symbol Description Reset
value
Access
11:0 MASK Selects interrupt on pin x to be masked (x = 0 to 11).
0 = Interrupt on pin PIOn_x is masked.
1 = Interrupt on pin PIOn_x is not masked.
0x00 R/W
31:12 - Reserved - -