Datasheet
UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 194 of 547
NXP Semiconductors
UM10398
Chapter 12: LPC111x/LPC11Cxx General Purpose I/O (GPIO)
12.3.8 GPIO masked interrupt status register
Bits read HIGH in the GPIOnMIS register reflect the status of the input lines triggering an
interrupt. Bits read as LOW indicate that either no interrupt on the corresponding input
pins has been generated or that the interrupt is masked. GPIOMIS is the state of the
interrupt after masking. The register is read-only.
12.3.9 GPIO interrupt clear register
This register allows software to clear edge detection for port bits that are identified as
edge-sensitive in the Interrupt Sense register. This register has no effect on port bits
identified as level-sensitive.
Table 180. GPIOnRIS register (GPIO0RIS, address 0x5000 8014 to GPIO3RIS, address 0x5003
8014) bit description
Bit Symbol Description Reset
value
Access
11:0 RAWST Raw interrupt status (x = 0 to 11).
0 = No interrupt on pin PIOn_x.
1 = Interrupt requirements met on PIOn_x.
0x00 R
31:12 - Reserved - -
Table 181. GPIOnMIS register (GPIO0MIS, address 0x5000 8018 to GPIO3MIS, address
0x5003 8018) bit description
Bit Symbol Description Reset
value
Access
11:0 MASK Selects interrupt on pin x to be masked (x = 0 to 11).
0 = No interrupt or interrupt masked on pin PIOn_x.
1 = Interrupt on PIOn_x.
0x00 R
31:12 - Reserved - -
Table 182. GPIOnIC register (GPIO0IC, address 0x5000 801C to GPIO3IC, address 0x5003
801C) bit description
Bit Symbol Description Reset
value
Access
11:0 CLR Selects interrupt on pin x to be cleared (x = 0 to 11). Clears
the interrupt edge detection logic. This register is write-only.
Remark: The synchronizer between the GPIO and the
NVIC blocks causes a delay of 2 clocks. It is recommended
to add two NOPs after the clear of the interrupt edge
detection logic before the exit of the interrupt service
routine.
0 = No effect.
1 = Clears edge detection logic for pin PIOn_x.
0x00 W
31:12 - Reserved - -