Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 198 of 547
NXP Semiconductors
UM10398
Chapter 13: LPC111x/LPC11Cxx UART
13.4 Pin description
[1] LQFP48 packages only.
The DSR, DCD, and RI modem inputs are multiplexed to two different pin locations. Use
the IOCON_LOC registers (see Section 7.4
) to select a physical location for each function
on the LQFP48 pin package in addition to selecting the function in the IOCON registers.
The DTR
output is available in two pin locations as well. The output value of the DTR pin
is driven in both locations identically, and the DTR
function at any location can be selected
simply by selecting the function in the IOCON register for that pin location.
13.5 Register description
The UART contains registers organized as shown in Table 184. The Divisor Latch Access
Bit (DLAB) is contained in U0LCR[7] and enables access to the Divisor Latches.
The reset value reflects the data stored in used bits only. It does not include the content of
reserved bits.
Table 183. UART pin description
Pin Type Description
RXD Input Serial Input. Serial receive data.
TXD Output Serial Output. Serial transmit data.
RTS
Output Request To Send. RS-485 direction control pin.
DTR
Output Data Terminal Ready.
DSR
[1]
Input Data Set Ready.
CTS
Input Clear To Send.
DCD
[1]
Input Data Carrier Detect.
RI
[1]
Input Ring Indicator.
Table 184. Register overview: UART (base address: 0x4000 8000)
Name Access Address
offset
Description Reset
value
U0RBR RO 0x000 Receiver Buffer Register. Contains the next received character to be read.
(DLAB=0)
NA
U0THR WO 0x000 Transmit Holding Register. The next character to be transmitted is written
here. (DLAB=0)
NA
U0DLL R/W 0x000 Divisor Latch LSB. Least significant byte of the baud rate divisor value. The
full divisor is used to generate a baud rate from the fractional rate divider.
(DLAB=1)
0x01
U0DLM R/W 0x004 Divisor Latch MSB. Most significant byte of the baud rate divisor value. The
full divisor is used to generate a baud rate from the fractional rate divider.
(DLAB=1)
0x00
U0IER R/W 0x004 Interrupt Enable Register. Contains individual interrupt enable bits for the 7
potential UART interrupts. (DLAB=0)
0x00
U0IIR RO 0x008 Interrupt ID Register. Identifies which interrupt(s) are pending. 0x01
U0FCR WO 0x008 FIFO Control Register. Controls UART FIFO usage and modes. 0x00