Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 204 of 547
NXP Semiconductors
UM10398
Chapter 13: LPC111x/LPC11Cxx UART
[1] Values “0000”, “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.
[2] For details see Section 13.5.9 “
UART Line Status Register (U0LSR - 0x4000 8014, Read Only)”
[3] For details see Section 13.5.1 “UART Receiver Buffer Register (U0RBR - 0x4000 8000, when DLAB = 0,
Read Only)”
[4] For details see Section 13.5.5 “UART Interrupt Identification Register (U0IIR - 0x4004 8008, Read Only)”
and Section 13.5.2 “
UART Transmitter Holding Register (U0THR - 0x4000 8000 when DLAB = 0, Write
Only)”
The UART THRE interrupt (U0IIR[3:1] = 001) is a third level interrupt and is activated
when the UART THR FIFO is empty provided certain initialization conditions have been
met. These initialization conditions are intended to give the UART THR FIFO a chance to
fill up with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit whenever
THRE = 1 and there have not been at least two characters in the U0THR at one time
since the last THRE = 1 event. This delay is provided to give the CPU time to write data to
U0THR without a THRE interrupt to decode and service. A THRE interrupt is set
immediately if the UART THR FIFO has held two or more characters at one time and
currently, the U0THR is empty. The THRE interrupt is reset when a U0THR write occurs or
a read of the U0IIR occurs and the THRE is the highest interrupt (U0IIR[3:1] = 001).
It is the lowest priority interrupt and is activated whenever there is any state change on
modem inputs pins, DCD, DSR or CTS. In addition, a low to high transition on modem
input RI will generate a modem interrupt. The source of the modem interrupt can be
determined by examining MSR[3:0]. A MSR read will clear the modem interrupt.
13.5.6 UART FIFO Control Register (U0FCR - 0x4000 8008, Write Only)
The U0FCR controls the operation of the UART RX and TX FIFOs.
1100 Second Character
Time-out
indication
Minimum of one character in the RX FIFO and no
character input or removed during a time period
depending on how many characters are in FIFO
and what the trigger level is set at (3.5 to 4.5
character times).
The exact time will be:
[(word length)  7 - 2]  8 + [(trigger level - number
of characters)  8 + 1] RCLKs
U0RBR
Read
[3]
0010 Third THRE THRE
[2]
U0IIR
Read
[4]
(if
source of
interrupt) or
THR write
0000 Fourth Modem
status
CTS or DSR or RI or DCD MSR read
Table 191. UART Interrupt Handling
U0IIR[3:0]
value
[1]
Priority Interrupt
type
Interrupt source Interrupt
reset