Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 210 of 547
NXP Semiconductors
UM10398
Chapter 13: LPC111x/LPC11Cxx UART
3 FE Framing Error. When the stop bit of a received character is a
logic 0, a framing error occurs. A U0LSR read clears
U0LSR[3]. The time of the framing error detection is
dependent on U0FCR0. Upon detection of a framing error, the
RX will attempt to re-synchronize to the data and assume that
the bad stop bit is actually an early start bit. However, it cannot
be assumed that the next received byte will be correct even if
there is no Framing Error.
Note: A framing error is associated with the character at the
top of the UART RBR FIFO.
0
0 Framing error status is inactive.
1 Framing error status is active.
4 BI Break Interrupt. When RXD1 is held in the spacing state (all
zeros) for one full character transmission (start, data, parity,
stop), a break interrupt occurs. Once the break condition has
been detected, the receiver goes idle until RXD1 goes to
marking state (all ones). A U0LSR read clears this status bit.
The time of break detection is dependent on U0FCR[0].
Note: The break interrupt is associated with the character at
the top of the UART RBR FIFO.
0
0 Break interrupt status is inactive.
1 Break interrupt status is active.
5 THRE Transmitter Holding Register Empty. THRE is set immediately
upon detection of an empty UART THR and is cleared on a
U0THR write.
1
0 U0THR contains valid data.
1 U0THR is empty.
6 TEMT Transmitter Empty. TEMT is set when both U0THR and
U0TSR are empty; TEMT is cleared when either the U0TSR or
the U0THR contain valid data. This bit is updated as soon as
50 % of the first stop bit has been transmitted or a byte has
been written into the THR.
1
0 U0THR and/or the U0TSR contains valid data.
1 U0THR and the U0TSR are empty.
7 RXFE Error in RX FIFO. U0LSR[7] is set when a character with a RX
error such as framing error, parity error or break interrupt, is
loaded into the U0RBR. This bit is cleared when the U0LSR
register is read and there are no subsequent errors in the
UART FIFO.
0
0 U0RBR contains no UART RX errors or U0FCR[0]=0.
1 UART RBR contains at least one UART RX error.
31:
8
- - Reserved -
Table 196. UART Line Status Register (U0LSR - address 0x4000 8014, Read Only) bit
description
…continued
Bit Symbol Value Description Reset
Value