Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 22 of 547
3.1 How to read this chapter
The following functions of the system configuration block depend on the specific part
number:
DEVICE_ID register
The DEVICE_ID register is valid 0x4004 83F4 for parts of the LPC1100, LPC1100C, and
LPC1100L series only.
The device ID cannot be read through the SYSCON block for the LPC1100XL series. Use
the ISP part ID command (Table 400
) to obtain the device ID for the LPC1100XL parts.
C_CAN controller
The C_CAN clock control bit 17 in the SYSAHBCLKCTRL register (Table 21
) and the
C_CAN reset control bit 3 in the PRESETCTRL register (Table 9
) are only functional for
parts LPC11Cxx/101/201/301.
Entering Deep power-down mode
Status of the IRC before entering Deep power-down mode (see Section 3.9.4.2
):
• IRC must be enabled for parts LPC111x/101/201/301 and parts
LPC11Cxx/101/201/301.
• IRC status has no effect for parts in the LPC1100L and LPC1100XL series.
Enabling sequence for UART clock
Requirements for enabling the UART peripheral clock:
• The UART pins must be configured in the IOCON block before the UART clock can be enabled
in the
in the SYSAHBCLKCTRL register (Table 21) for parts LPC111x/101/201/301.
• The sequence of configuring the UART pins and the UART clock has no effect for
parts in the LPC1100L and LPC1100XL series and parts LPC1100C series.
NMI source selection register
The NMI source selection register is only available on parts in the LPC1100XL series.
3.2 General description
The system configuration block controls oscillators, start logic, and clock generation of the
LPC111x/LPC11Cxx. Also included in this block is a register for remapping flash, SRAM,
and ROM memory areas.
3.3 Pin description
Table 6 shows pins that are associated with system control block functions.
UM10398
Chapter 3: LPC111x/LPC11Cxx System configuration
(SYSCON)
Rev. 12.3 — 10 June 2014 User manual