Datasheet
UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 220 of 547
NXP Semiconductors
UM10398
Chapter 13: LPC111x/LPC11Cxx UART
13.5.18 UART RS485 Address Match register (U0RS485ADRMATCH - 0x4000
8050)
The U0RS485ADRMATCH register contains the address match value for RS-485/EIA-485
mode.
13.5.19 UART1 RS485 Delay value register (U0RS485DLY - 0x4000 8054)
The user may program the 8-bit RS485DLY register with a delay between the last stop bit
leaving the TXFIFO and the de-assertion of RTS
(or DTR). This delay time is in periods of
the baud clock. Any delay time from 0 to 255 bit times may be programmed.
13.5.20 RS-485/EIA-485 modes of operation
The RS-485/EIA-485 feature allows the UART to be configured as an addressable slave.
The addressable slave is one of multiple slaves controlled by a single master.
4 DCTRL Auto direction control enable. 0
0 Disable Auto Direction Control.
1 Enable Auto Direction Control.
5 OINV Polarity control. This bit reverses the polarity of
the direction control signal on the RTS
(or DTR)
pin.
0
0 The direction control pin will be driven to logic 0
when the transmitter has data to be sent. It will be
driven to logic 1 after the last bit of data has been
transmitted.
1 The direction control pin will be driven to logic 1
when the transmitter has data to be sent. It will be
driven to logic 0 after the last bit of data has been
transmitted.
31:6 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit
is not defined.
NA
Table 203. UART RS485 Control register (U0RS485CTRL - address 0x4000 804C) bit
description
…continued
Bit Symbol Value Description Reset
value
Table 204. UART RS485 Address Match register (U0RS485ADRMATCH - address
0x4000 8050) bit description
Bit Symbol Description Reset value
7:0 ADRMATCH Contains the address match value. 0x00
31:8 - Reserved -
Table 205. UART RS485 Delay value register (U0RS485DLY - address 0x4000 8054) bit
description
Bit Symbol Description Reset value
7:0 DLY Contains the direction control (RTS or DTR) delay value. This
register works in conjunction with an 8-bit counter.
0x00
31:8 - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
NA