Datasheet
UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 224 of 547
14.1 How to read this chapter
The SPI blocks are identical for all LPC111x, LPC11D14, and LPC11Cxx parts. The
second SPI block, SPI1, is available on LQFP48 packages.
For parts in the LPC1100 and LPC1100L series, SPI1 is not available on HVQFN33
packages.
For parts in the LPC1100XL series, SPI1 is supported on all packages.
Remark: Both SPI blocks include the full SSP feature set, and all register names use the
SSP prefix.
14.2 Basic configuration
The SPI0/1 are configured using the following registers:
1. Pins: The SPI pins must be configured in the IOCONFIG register block. In addition,
use the IOCON_LOC register (see Section 7.4
) to select a location for the SCK0
function.
2. Power: In the SYSAHBCLKCTRL register, set bit 11 and bit 18 (Table 21
).
3. Peripheral clock: Enable the SPI0/1 peripheral clock by writing to the SSP0/1CLKDIV
registers (Section 3.5.15
and Section 3.5.17).
4. Reset: Before accessing the SPI blocks, ensure that the SSP_RST_N bits (bit 0 and
bit 2) in the PRESETCTRL register (Table 9
) is set to 1. This de-asserts the reset
signal to the SPI blocks.
14.3 Features
• Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses.
• Synchronous Serial Communication.
• Supports master or slave operation.
• Eight-frame FIFOs for both transmit and receive.
• 4-bit to 16-bit frame.
14.4 General description
The SPI/SSP is a Synchronous Serial Port (SSP) controller capable of operation on a SPI,
4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus.
Only a single master and a single slave can communicate on the bus during a given data
transfer. Data transfers are in principle full duplex, with frames of 4 bits to 16 bits of data
flowing from the master to the slave and from the slave to the master. In practice it is often
the case that only one of these data flows carries meaningful data.
UM10398
Chapter 14: LPC111x/LPC11Cxx SPI0/1 with SSP
Rev. 12.3 — 10 June 2014 User manual