Datasheet

User manual Rev. 12.3 — 10 June 2014 226 of 547

NXP Semiconductors

UM10398

Chapter 14: LPC111x/LPC11Cxx SPI0/1 with SSP

14.6 Register description

The register addresses of the SPI controllers are shown in Table 207 and Table 208.

The reset value reflects the data stored in used bits only. It does not include the content of

reserved bits.

Remark: Register names use the SSP prefix to indicate that the SPI controllers have full

SSP capabilities.

14.6.1 SPI/SSP Control Register 0

This register controls the basic operation of the SPI/SSP controller.

Table 207. Register overview: SPI0 (base address 0x4004 0000)

Name Access Address

offset

Description Reset

value

SSP0CR0 R/W 0x000 Control Register 0. Selects the serial clock rate, bus type, and data size. 0

SSP0CR1 R/W 0x004 Control Register 1. Selects master/slave and other modes. 0

SSP0DR R/W 0x008 Data Register. Writes fill the transmit FIFO, and reads empty the receive

FIFO.

SSP0SR RO 0x00C Status Register 0x0000

0003

SSP0CPSR R/W 0x010 Clock Prescale Register 0

SSP0IMSC R/W 0x014 Interrupt Mask Set and Clear Register 0

SSP0RIS RO 0x018 Raw Interrupt Status Register 0x0000

0008

SSP0MIS RO 0x01C Masked Interrupt Status Register 0

SSP0ICR WO 0x020 SSPICR Interrupt Clear Register NA

Table 208. Register overview: SPI1 (base address 0x4005 8000)

Name Access Address

offset

Description Reset

value

SSP1CR0 R/W 0x000 Control Register 0. Selects the serial clock rate, bus type, and data size. 0

SSP1CR1 R/W 0x004 Control Register 1. Selects master/slave and other modes. 0

SSP1DR R/W 0x008 Data Register. Writes fill the transmit FIFO, and reads empty the receive