Datasheet
UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 231 of 547
NXP Semiconductors
UM10398
Chapter 14: LPC111x/LPC11Cxx SPI0/1 with SSP
14.6.9 SPI/SSP Interrupt Clear Register
Software can write one or more one(s) to this write-only register, to clear the
corresponding interrupt condition(s) in the SPI controller. Note that the other two interrupt
conditions can be cleared by writing or reading the appropriate FIFO or disabled by
clearing the corresponding bit in SSPIMSC registers.
14.7 Functional description
14.7.1 Texas Instruments synchronous serial frame format
Figure 37 shows the 4-wire Texas Instruments synchronous serial frame format supported
by the SPI module.
Table 216: SPI/SSP Masked Interrupt Status register (SSP0MIS - address 0x4004 001C,
SSP1MIS - address 0x4005 801C) bit description
Bit Symbol Description Reset Value
0 RORMIS This bit is 1 if another frame was completely received while the
RxFIFO was full, and this interrupt is enabled.
0
1 RTMIS This bit is 1 if the Rx FIFO is not empty, has not been read for
a time-out period, and this interrupt is enabled. The time-out
period is the same for master and slave modes and is
determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR
[SCR+1]).
0
2 RXMIS This bit is 1 if the Rx FIFO is at least half full, and this interrupt
is enabled.
0
3 TXMIS This bit is 1 if the Tx FIFO is at least half empty, and this
interrupt is enabled.
0
31:4 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
NA
Table 217: SPI/SSP interrupt Clear Register (SSP0ICR - address 0x4004 0020, SSP1ICR -
address 0x4005 8020) bit description
Bit Symbol Description Reset Value
0 RORIC Writing a 1 to this bit clears the “frame was received when
RxFIFO was full” interrupt.
NA
1 RTIC Writing a 1 to this bit clears the Rx FIFO was not empty and
has not been read for a timeout period interrupt. The timeout
period is the same for master and slave modes and is
determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR
[SCR+1]).
NA
31:2 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
NA