Datasheet

User manual Rev. 12.3 — 10 June 2014 238 of 547

NXP Semiconductors

UM10398

Chapter 14: LPC111x/LPC11Cxx SPI0/1 with SSP

turn latches each bit on the rising edge of SK. At the end of the frame, for single transfers,

the CS signal is pulled HIGH one clock period after the last bit has been latched in the

receive serial shifter, that causes the data to be transferred to the receive FIFO.

Note: The off-chip slave device can tristate the receive line either on the falling edge of

SK after the LSB has been latched by the receive shiftier, or when the CS pin goes HIGH.

For continuous transfers, data transmission begins and ends in the same manner as a

single transfer. However, the CS line is continuously asserted (held LOW) and

transmission of data occurs back to back. The control byte of the next frame follows

directly after the LSB of the received data from the current frame. Each of the received

values is transferred from the receive shifter on the falling edge SK, after the LSB of the

frame has been latched into the SPI/SSP.

14.7.3.1 Setup and hold time requirements on CS with respect to SK in Microwire

mode

In the Microwire mode, the SPI/SSP slave samples the first bit of receive data on the

rising edge of SK after CS has gone LOW. Masters that drive a free-running SK must

ensure that the CS signal has sufficient setup and hold margins with respect to the rising

edge of SK.

Figure 44

illustrates these setup and hold time requirements. With respect to the SK rising

edge on which the first bit of receive data is to be sampled by the SPI/SSP slave, CS must

have a setup of at least two times the period of SK on which the SPI/SSP operates. With

respect to the SK rising edge previous to this edge, CS must have a hold of at least one

SK period.

Fig 44. Microwire frame format setup and hold details

HOLD

= t

SETUP

=2*t