Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 239 of 547
15.1 How to read this chapter
The I
2
C-bus block is identical for all LPC111x, LPC11D14, and LPC11Cxx parts.
The I2C-bus is interface is not available on part LPC1112FDH20/102.
15.2 Basic configuration
The I
2
C-bus interface is configured using the following registers:
1. Pins: The I2C pin functions and the I2C mode are configured in the IOCONFIG
register block (Section 7.4
, Table 68 and Table 69).
2. Power and peripheral clock: In the SYSAHBCLKCTRL register, set bit 5 (Table 21
).
3. Reset: Before accessing the I2C block, ensure that the I2C_RST_N bit (bit 1) in the
PRESETCTRL register (Table 9
) is set to 1. This de-asserts the reset signal to the I2C
block.
15.3 Features
• Standard I
2
C-compliant bus interfaces may be configured as Master, Slave, or
Master/Slave.
• Arbitration is handled between simultaneously transmitting masters without corruption
of serial data on the bus.
• Programmable clock allows adjustment of I
2
C transfer rates.
• Data transfer is bidirectional between masters and slaves.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization is used as a handshake mechanism to suspend and
resume serial transfer.
• Supports Fast-mode Plus.
• Optional recognition of up to four distinct slave addresses.
• Monitor mode allows observing all I
2
C-bus traffic, regardless of slave address.
• I
2
C-bus can be used for test and diagnostic purposes.
• The I
2
C-bus contains a standard I
2
C-compliant bus interface with two pins.
15.4 Applications
Interfaces to external I
2
C standard parts, such as serial RAMs, LCDs, tone generators,
other microcontrollers, etc.
UM10398
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
Rev. 12.3 — 10 June 2014 User manual