Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 24 of 547
NXP Semiconductors
UM10398
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
3.5 Register description
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
See Section 3.12
for the flash access timing register, which can be re-configured as part
the system setup. This register is not part of the system configuration block.
Fig 8. LPC111x/LPC11Cxx CGU block diagram
SYSTEM PLL
IRC oscillator
system oscillator
watchdog oscillator
IRC oscillator
watchdog oscillator
MAINCLKSEL
(main clock select)
SYSPLLCLKSEL
(system PLL clock select)
SYSTEM CLOCK
DIVIDER
SYSAHBCLKCTRL[1:18]
SPI0 PERIPHERAL
CLOCK DIVIDER
SPI0_PCLK
SPI1 PERIPHERAL
CLOCK DIVIDER
SPI1_PCLK
UART PERIPHERAL
CLOCK DIVIDER
UART_PCLK
WDT CLOCK
DIVIDER
WDCLK
WDTUEN
(WDT clock update enable)
watchdog oscillator
IRC oscillator
system oscillator
CLKOUT PIN CLOCK
DIVIDER
CLKOUT pin
CLKOUTUEN
(CLKOUT update enable)
main clock
system clock
IRC oscillator
AHB clocks
1 to 18
(memories
and peripherals)
18
sys_pllclkout
sys_pllclkin
ARM
CORTEX-M0
SYSAHBCLKDIV
Table 7. Register overview: system control block (base address 0x4004 8000)
Name Access Address offset Description Reset
value
Reference
SYSMEMREMAP R/W 0x000 System memory remap 0x002 Table 8
PRESETCTRL R/W 0x004 Peripheral reset control 0x000 Table 9
SYSPLLCTRL R/W 0x008 System PLL control 0x000 Table 10
SYSPLLSTAT R 0x00C System PLL status 0x000 Table 11
- - 0x010 - 0x01C Reserved - -