Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 244 of 547
NXP Semiconductors
UM10398
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
The AA bit can be cleared by writing 1 to the AAC bit in the CONCLR register. When AA is
0, a not acknowledge (HIGH level to SDA) will be returned during the acknowledge clock
pulse on the SCL line on the following situations:
1. A data byte has been received while the I
2
C is in the master receiver mode.
2. A data byte has been received while the I
2
C is in the addressed slave receiver mode.
15.7.2 I
2
C Status register (I2C0STAT - 0x4000 0004)
Each I
2
C Status register reflects the condition of the corresponding I
2
C interface. The I
2
C
Status register is Read-Only.
The three least significant bits are always 0. Taken as a byte, the status register contents
represent a status code. There are 26 possible status codes. When the status code is
0xF8, there is no relevant information available and the SI bit is not set. All other 25 status
codes correspond to defined I
2
C states. When any of these states entered, the SI bit will
be set. For a complete list of status codes, refer to tables from Table 236
to Table 241.
15.7.3 I
2
C Data register (I2C0DAT - 0x4000 0008)
This register contains the data to be transmitted or the data just received. The CPU can
read and write to this register only while it is not in the process of shifting a byte, when the
SI bit is set. Data in DAT register remains stable as long as the SI bit is set. Data in DAT
register is always shifted from right to left: the first bit to be transmitted is the MSB (bit 7),
and after a byte has been received, the first bit of received data is located at the MSB of
the DAT register.
15.7.4 I
2
C Slave Address register 0 (I2C0ADR0- 0x4000 000C)
This register is readable and writable and are only used when an I
2
C interface is set to
slave mode. In master mode, this register has no effect. The LSB of the ADR register is
the General Call bit. When this bit is set, the General Call address (0x00) is recognized.
If this register contains 0x00, the I
2
C will not acknowledge any address on the bus. All four
registers (ADR0 to ADR3) will be cleared to this disabled state on reset. See also
Table 229
.
Table 221. I
2
C Status register (I2C0STAT - 0x4000 0004) bit description
Bit Symbol Description Reset value
2:0 - These bits are unused and are always 0. 0
7:3 Status These bits give the actual status information about the I
2
C
interface.
0x1F
31:8 - Reserved. The value read from a reserved bit is not defined. -
Table 222. I
2
C Data register (I2C0DAT - 0x4000 0008) bit description
Bit Symbol Description Reset value
7:0 Data This register holds data values that have been received or are to
be transmitted.
0
31:8 - Reserved. The value read from a reserved bit is not defined. -