Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 247 of 547
NXP Semiconductors
UM10398
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
[1] When the ENA_SCL bit is cleared and the I
2
C no longer has the ability to stall the bus, interrupt response
time becomes important. To give the part more time to respond to an I
2
C interrupt under these conditions, a
DATA _BUFFER register is used (Section 15.7.9
) to hold received data for a full 9-bit word transmission
time.
Remark: The ENA_SCL and MATCH_ALL bits have no effect if the MM_ENA is ‘0’ (i.e. if
the module is NOT in monitor mode).
15.7.7.1 Interrupt in Monitor mode
All interrupts will occur as normal when the module is in monitor mode. This means that
the first interrupt will occur when an address-match is detected (any address received if
the MATCH_ALL bit is set, otherwise an address matching one of the four address
registers).
Subsequent to an address-match detection, interrupts will be generated after each data
byte is received for a slave-write transfer, or after each byte that the module “thinks” it has
transmitted for a slave-read transfer. In this second case, the data register will actually
contain data transmitted by some other slave on the bus which was actually addressed by
the master.
Table 228. I
2
C Monitor mode control register (I2C0MMCTRL - 0x4000 001C) bit description
Bit Symbol Value Description Reset
value
0 MM_ENA Monitor mode enable. 0
0 Monitor mode disabled.
1The I
2
C module will enter monitor mode. In this mode the
SDA output will be forced high. This will prevent the I
2
C
module from outputting data of any kind (including ACK)
onto the I
2
C data bus.
Depending on the state of the ENA_SCL bit, the output may
be also forced high, preventing the module from having
control over the I
2
C clock line.
1 ENA_SCL SCL output enable. 0
0 When this bit is cleared to ‘0’, the SCL output will be forced
high when the module is in monitor mode. As described
above, this will prevent the module from having any control
over the I
2
C clock line.
1 When this bit is set, the I
2
C module may exercise the same
control over the clock line that it would in normal operation.
This means that, acting as a slave peripheral, the I
2
C
module can “stretch” the clock line (hold it low) until it has
had time to respond to an I
2
C interrupt.
[1]
2 MATCH_ALL Select interrupt register match. 0
0 When this bit is cleared, an interrupt will only be generated
when a match occurs to one of the (up-to) four address
registers described above. That is, the module will respond
as a normal slave as far as address-recognition is
concerned.
1 When this bit is set to ‘1’ and the I
2
C is in monitor mode, an
interrupt will be generated on ANY address received. This
will enable the part to monitor all traffic on the bus.
31:3 - - Reserved. The value read from reserved bits is not defined.