Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 248 of 547
NXP Semiconductors
UM10398
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
Following all of these interrupts, the processor may read the data register to see what was
actually transmitted on the bus.
15.7.7.2 Loss of arbitration in Monitor mode
In monitor mode, the I
2
C module will not be able to respond to a request for information by
the bus master or issue an ACK). Some other slave on the bus will respond instead. This
will most probably result in a lost-arbitration state as far as our module is concerned.
Software should be aware of the fact that the module is in monitor mode and should not
respond to any loss of arbitration state that is detected. In addition, hardware may be
designed into the module to block some/all loss of arbitration states from occurring if those
state would either prevent a desired interrupt from occurring or cause an unwanted
interrupt to occur. Whether any such hardware will be added is still to be determined.
15.7.8 I
2
C Slave Address registers (I2C0ADR[1, 2, 3] - 0x4000 00[20, 24, 28])
These registers are readable and writable and are only used when an I
2
C interface is set
to slave mode. In master mode, this register has no effect. The LSB of the ADR register is
the General Call bit. When this bit is set, the General Call address (0x00) is recognized.
If these registers contain 0x00, the I
2
C will not acknowledge any address on the bus. All
four registers will be cleared to this disabled state on reset (also see Table 223
).
15.7.9 I
2
C Data buffer register (I2C0DATA_BUFFER - 0x4000 002C)
In monitor mode, the I
2
C module may lose the ability to stretch the clock (stall the bus) if
the ENA_SCL bit is not set. This means that the processor will have a limited amount of
time to read the contents of the data received on the bus. If the processor reads the DAT
shift register, as it ordinarily would, it could have only one bit-time to respond to the
interrupt before the received data is overwritten by new data.
To give the processor more time to respond, a new 8-bit, read-only DATA_BUFFER
register will be added. The contents of the 8 MSBs of the DAT shift register will be
transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus
ACK or NACK) has been received on the bus. This means that the processor will have
nine bit transmission times to respond to the interrupt and read the data before it is
overwritten.
The processor will still have the ability to read the DAT register directly, as usual, and the
behavior of DAT will not be altered in any way.
Although the DATA_BUFFER register is primarily intended for use in monitor mode with
the ENA_SCL bit = ‘0’, it will be available for reading at any time under any mode of
operation.
Table 229. I
2
C Slave Address registers (I2C0ADR[1, 2, 3]- 0x4000 00[20, 24, 28]) bit
description
Bit Symbol Description Reset value
0 GC General Call enable bit. 0
7:1 Address The I
2
C device address for slave mode. 0x00
31:8 - Reserved. The value read from a reserved bit is not defined. 0