Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 249 of 547
NXP Semiconductors
UM10398
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
15.7.10 I
2
C Mask registers (I2C0MASK[0, 1, 2, 3] - 0x4000 00[30, 34, 38, 3C])
The four mask registers each contain seven active bits (7:1). Any bit in these registers
which is set to ‘1’ will cause an automatic compare on the corresponding bit of the
received address when it is compared to the ADDRn register associated with that mask
register. In other words, bits in an ADDRn register which are masked are not taken into
account in determining an address match.
On reset, all mask register bits are cleared to ‘0’.
The mask register has no effect on comparison to the General Call address (“0000000”).
Bits(31:8) and bit(0) of the mask registers are unused and should not be written to. These
bits will always read back as zeros.
When an address-match interrupt occurs, the processor will have to read the data register
(DAT) to determine what the received address was that actually caused the match.
15.8 I
2
C operating modes
In a given application, the I
2
C block may operate as a master, a slave, or both. In the slave
mode, the I
2
C hardware looks for any one of its four slave addresses and the General Call
address. If one of these addresses is detected, an interrupt is requested. If the processor
wishes to become the bus master, the hardware waits until the bus is free before the
master mode is entered so that a possible slave operation is not interrupted. If bus
arbitration is lost in the master mode, the I
2
C block switches to the slave mode
immediately and can detect its own slave address in the same serial transfer.
15.8.1 Master Transmitter mode
In this mode data is transmitted from master to slave. Before the master transmitter mode
can be entered, the CONSET register must be initialized as shown in Table 232
. I2EN
must be set to 1 to enable the I
2
C function. If the AA bit is 0, the I
2
C interface will not
acknowledge any address when another device is master of the bus, so it can not enter
slave mode. The STA, STO and SI bits must be 0. The SI Bit is cleared by writing 1 to the
SIC bit in the CONCLR register. THe STA bit should be cleared after writing the slave
address.
Table 230. I
2
C Data buffer register (I2C0DATA_BUFFER - 0x4000 002C) bit description
Bit Symbol Description Reset value
7:0 Data This register holds contents of the 8 MSBs of the DAT shift
register.
0
31:8 - Reserved. The value read from a reserved bit is not defined. 0
Table 231. I
2
C Mask registers (I2C0MASK[0, 1, 2, 3] - 0x4000 00[30, 34, 38, 3C]) bit
description
Bit Symbol Description Reset value
0 - Reserved. User software should not write ones to reserved
bits. This bit reads always back as 0.
0
7:1 MASK Mask bits. 0x00
31:8 - Reserved. The value read from reserved bits is undefined. 0