Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 256 of 547
NXP Semiconductors
UM10398
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
via the I
2
C Clock Control Registers. See the description of the I2CSCLL and I2CSCLH
registers for details. The output clock pulses have a duty cycle as programmed unless the
bus is synchronizing with other SCL clock sources as described above.
15.9.8 Timing and control
The timing and control logic generates the timing and control signals for serial byte
handling. This logic block provides the shift pulses for DAT, enables the comparator,
generates and detects START and STOP conditions, receives and transmits acknowledge
bits, controls the master and slave modes, contains interrupt request logic, and monitors
the I
2
C-bus status.
15.9.9 Control register, CONSET and CONCLR
The I
2
C control register contains bits used to control the following I
2
C block functions: start
and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition,
and acknowledgment.
The contents of the I
2
C control register may be read as CONSET. Writing to CONSET will
set bits in the I
2
C control register that correspond to ones in the value written. Conversely,
writing to CONCLR will clear bits in the I
2
C control register that correspond to ones in the
value written.
15.9.10 Status decoder and status register
The status decoder takes all of the internal status bits and compresses them into a 5-bit
code. This code is unique for each I
2
C-bus status. The 5-bit code may be used to
generate vector addresses for fast processing of the various service routines. Each
service routine processes a particular bus status. There are 26 possible bus states if all
four modes of the I
2
C block are used. The 5-bit status code is latched into the five most
significant bits of the status register when the serial interrupt flag is set (by hardware) and
remains stable until the interrupt flag is cleared by software. The three least significant bits
of the status register are always zero. If the status code is used as a vector to service
routines, then the routines are displaced by eight address locations. Eight bytes of code is
sufficient for most of the service routines (see the software example in this section).
15.10 Details of I
2
C operating modes
The four operating modes are:
• Master Transmitter
• Master Receiver
• Slave Receiver
• Slave Transmitter
Data transfers in each mode of operation are shown in Figure 54
, Figure 55, Figure 56,
Figure 57
, and Figure 58. Table 234 lists abbreviations used in these figures when
describing the I
2
C operating modes.