Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 258 of 547
NXP Semiconductors
UM10398
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
The master transmitter mode may now be entered by setting the STA bit. The I
2
C logic will
now test the I
2
C-bus and generate a START condition as soon as the bus becomes free.
When a START condition is transmitted, the serial interrupt flag (SI) is set, and the status
code in the status register (STAT) will be 0x08. This status code is used by the interrupt
service routine to enter the appropriate state service routine that loads DAT with the slave
address and the data direction bit (SLA+W). The SI bit in CON must then be reset before
the serial transfer can continue.
When the slave address and the direction bit have been transmitted and an
acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a
number of status codes in STAT are possible. There are 0x18, 0x20, or 0x38 for the
master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = logic 1).
The appropriate action to be taken for each of these status codes is detailed in Table 236
.
After a Repeated START condition (state 0x10). The I
2
C block may switch to the master
receiver mode by loading DAT with SLA+R).