Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 27 of 547
NXP Semiconductors
UM10398
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
3.5.3 System PLL control register
This register connects and enables the system PLL and configures the PLL multiplier and
divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various
clock sources. The input frequency is multiplied up to a high frequency, then divided down
to provide the actual clock used by the CPU, peripherals, and memories. The PLL can
produce a clock up to the maximum allowed for the CPU.
3.5.4 System PLL status register
This register is a Read-only register and supplies the PLL lock status (see Section 3.11.1).
Table 9. Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit
description
Bit Symbol Value Description Reset
value
0 SSP0_RST_N SPI0 reset control 0
0 Resets the SPI0 peripheral.
1 SPI0 reset de-asserted.
1 I2C_RST_N I2C reset control 0
0 Resets the I2C peripheral.
1 I2C reset de-asserted.
2 SSP1_RST_N SPI1 reset control 0
0 Resets the SPI1 peripheral.
1 SPI1 reset de-asserted.
3 CAN_RST_N C_CAN reset control. See Section 3.1
for part specific
details.
0
0 Resets the C_CAN peripheral.
1 C_CAN reset de-asserted.
31:4 - - Reserved 0x00
Table 10. System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description
Bit Symbol Value Description Reset
value
4:0 MSEL Feedback divider value. The division value M is the
programmed MSEL value + 1.
00000: Division ratio M = 1
to
11111: Division ratio M = 32.
0x000
6:5 PSEL Post divider ratio P. The division ratio is 2 P. 0x00
0x0 P = 1
0x1 P = 2
0x2 P = 4
0x3 P = 8
31:7 - - Reserved. Do not write ones to reserved bits. 0x0