Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 271 of 547
NXP Semiconductors
UM10398
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
causes the I
2
C block to enter the “not addressed” slave mode (a defined state) and to
clear the STO flag (no other bits in CON are affected). The SDA and SCL lines are
released (a STOP condition is not transmitted).
15.10.6 Some special cases
The I
2
C hardware has facilities to handle the following special cases that may occur
during a serial transfer:
• Simultaneous Repeated START conditions from two masters
• Data transfer after loss of arbitration
• Forced access to the I
2
C-bus
• I
2
C-bus obstructed by a LOW level on SCL or SDA
• Bus error
15.10.6.1 Simultaneous Repeated START conditions from two masters
A Repeated START condition may be generated in the master transmitter or master
receiver modes. A special case occurs if another master simultaneously generates a
Repeated START condition (see Figure 58
). Until this occurs, arbitration is not lost by
either master since they were both transmitting the same data.
If the I
2
C hardware detects a Repeated START condition on the I
2
C-bus before generating
a Repeated START condition itself, it will release the bus, and no interrupt request is
generated. If another master frees the bus by generating a STOP condition, the I
2
C block
will transmit a normal START condition (state 0x08), and a retry of the total serial data
transfer can commence.
Table 242. Miscellaneous States
Status
Code
(STAT)
Status of the I
2
C-bus
and hardware
Application software response Next action taken by I
2
C hardware
To/From DAT To CON
STA STO SI AA
0xF8 No relevant state
information available;
SI = 0.
No DAT action No CON action Wait or proceed current transfer.
0x00 Bus error during MST
or selected slave
modes, due to an
illegal START or
STOP condition. State
0x00 can also occur
when interference
causes the I
2
C block
to enter an undefined
state.
No DAT action 0 1 0 X Only the internal hardware is affected in
the MST or addressed SLV modes. In all
cases, the bus is released and the I
2
C
block is switched to the not addressed
SLV mode. STO is reset.