Datasheet

User manual Rev. 12.3 — 10 June 2014 282 of 547

16.1 How to read this chapter

The C_CAN block is available in LPC11Cxx parts only (LPC11C00 series).

The LPC11C22 and LPC11C24 parts include an on-chip, high-speed transceiver. For

these parts, the CAN_RXD and CAN_TXD signals are connected internally to the on-chip

transceiver and the transceiver signals are pinned out (see Table 244

16.2 Basic configuration

The C_CAN is configured using the following registers:

1. Power: In the SYSAHBCLKCTRL register, set bit 17 (Table 21

2. Clocking: For an accurate peripheral clock to the C_CAN block, select the system

oscillator either as the main clock (Table 18

) or as input to the system PLL (Table 16).

Do not select the IRC if C_CAN baud rates above 100 kbit/s are required.

3. Reset: Before accessing the C_CAN block, ensure that the CAN_RST_N bit (bit 3) in

the PRESETCTRL register (Table 9

) is set to 1. This de-asserts the reset signal to the

C_CAN block.

The peripheral clock to the C_CAN (the C_CAN system clock) and to the programmable

C_CAN clock divider (see Table 275

) is provided by the system clock (seeTable 21). This

clock can be disabled through bit 17 in the SYSAHBCLKCTRL register for power savings.

Remark: If C_CAN baudrates above 100 kbit/s are required, the system oscillator must

be selected as the clock source for the system clock. For lower baudrates, the IRC may

also be used as clock source.

16.3 Features

• Conforms to protocol version 2.0 parts A and B.

• Supports bit rate of up to 1 Mbit/s.

• Supports 32 Message Objects.

• Each Message Object has its own identifier mask.

• Provides programmable FIFO mode (concatenation of Message Objects).

• Provides maskable interrupts.

• Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN

applications.

• Provides programmable loop-back mode for self-test operation.

UM10398

Chapter 16: LPC111x/LPC11Cxx C_CAN controller

Rev. 12.3 — 10 June 2014 User manual