Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 286 of 547
NXP Semiconductors
UM10398
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
16.6.1 CAN protocol registers
16.6.1.1 CAN control register
The reset value 0x0001 of the CANCTL register enables initialization by software (INIT =
1). The C_CAN does not influence the CAN bus until the CPU resets the INIT bit to 0.
Table 246. CAN control registers (CANCNTL, address 0x4005 0000) bit description
Bit Symbol Value Description Reset
value
Access
0 INIT Initialization 1 R/W
0 Normal operation.
1 Started. Initialization is started. On reset,
software needs to initialize the CAN controller.
1 IE Module interrupt enable 0 R/W
0 Disable CAN interrupts. The interrupt line is
always HIGH.
1 Enable CAN interrupts. The interrupt line is set
to LOW and remains LOW until all pending
interrupts are cleared.
2 SIE Status change interrupt enable 0 R/W
0 Disable status change interrupts. No status
change interrupt will be generated.
1 Enable status change interrupts. A status
change interrupt will be generated when a
message transfer is successfully completed or
a CAN bus error is detected.
3 EIE Error interrupt enable 0 R/W
0 Disable error interrupt. No error status interrupt
will be generated.
1 Enable error interrupt. A change in the bits
BOFF or EWARN in the CANSTAT registers
will generate an interrupt.
4 - - reserved 0 -
5 DAR Disable automatic retransmission 0 R/W
0 Enabled. Automatic retransmission of
disturbed messages enabled.
1 Disabled. Automatic retransmission disabled.
6 CCE Configuration change enable 0 R/W
0 No write access. The CPU has no write access
to the bit timing register.
1 Write access. The CPU has write access to the
CANBT register while the INIT bit is one.
7 TEST Test mode enable 0 R/W
0 Normal operation.
1 Test mode.
31:8 - reserved - -