Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 288 of 547
NXP Semiconductors
UM10398
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
Table 247. CAN status register (CANSTAT, address 0x4005 0004) bit description
Bit Symbol Value Description Reset
value
Access
2:0 LEC Last error code
Type of the last error to occur on the CAN bus.The LEC field holds a
code which indicates the type of the last error to occur on the CAN bus.
This field will be cleared to ‘0’ when a message has been transferred
(reception or transmission) without error. The unused code ‘111’ may be
written by the CPU to check for updates.
000 R/W
0x0 No error.
0x1 Stuff error. More than 5 equal bits in a sequence have occurred in a
part of a received message where this is not allowed.
0x2 Form error. A fixed format part of a received frame has the wrong
format.
0x3 AckError. The message this CAN core transmitted was not
acknowledged.
0x4 Bit1Error. During the transmission of a message (with the exception of
the arbitration field), the device wanted to send a HIGH/recessive level
(bit of logical value ‘1’), but the monitored bus value was
LOW/dominant.
0x5 Bit0Error. During the transmission of a message (or acknowledge bit,
or active error flag, or overload flag), the device wanted to send a
LOW/dominant level (data or identifier bit logical value ‘0’), but the
monitored Bus value was HIGH/recessive. During busoff recovery this
status is set each time a sequence of 11 HIGH/recessive bits has been
monitored. This enables the CPU to monitor the proceeding of the
busoff recovery sequence (indicating the bus is not stuck at
LOW/dominant or continuously disturbed).
0x6 CRCError. The CRC checksum was incorrect in the message received.
0x7 Unused. No CAN bus event was detected (written by the CPU).
3 TXOK Transmitted a message successfully
This bit must be reset by the CPU. It is never reset by the CAN
controller.
0R/W
0 No transmit. Since this bit was last reset by the CPU, no message has
been successfully transmitted.
1 Successful transmit. Since this bit was last reset by the CPU, a
message has been successfully transmitted (error free and
acknowledged by at least one other node).
4 RXOK Received a message successfully
This bit must be reset by the CPU. It is never reset by the CAN
controller.
0R/W
0 No receive. Since this bit was last reset by the CPU, no message has
been successfully received.
1 Successful receive.Since this bit was last set to zero by the CPU, a
message has been successfully received independent of the result of
acceptance filtering.