Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 29 of 547
NXP Semiconductors
UM10398
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
3.5.7 Internal resonant crystal control register
This register is used to trim the on-chip 12 MHz oscillator. The trim value is factory-preset
and written by the boot code on start-up.
3.5.8 System reset status register
The SYSRSTSTAT register shows the source of the latest reset event. Write a one to
clear the reset.
The POR event clears all other bits in this register. If any reset signal - for example
EXTRST - remains asserted after the POR signal is negated, then its bit is set to detected
in this register.
Table 13. Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit
description
Bit Symbol Value Description Reset
value
4:0 DIVSEL Select divider for Fclkana.
wdt_osc_clk = Fclkana/ (2  (1 + DIVSEL))
00000: 2  (1 + DIVSEL) = 2
00001: 2  (1 + DIVSEL) = 4
to
11111: 2  (1 + DIVSEL) = 64
0
8:5 FREQSEL Select watchdog oscillator analog output frequency
(Fclkana).
0x00
0x1 0.6 MHz
0x2 1.05 MHz
0x3 1.4 MHz
0x4 1.75 MHz
0x5 2.1 MHz
0x6 2.4 MHz
0x7 2.7 MHz
0x8 3.0 MHz
0x9 3.25 MHz
0xA 3.5 MHz
0xB 3.75 MHz
0xC 4.0 MHz
0xD 4.2 MHz
0xE 4.4 MHz
0xF 4.6 MHz
31:9 - - Reserved 0x00
Table 14. Internal resonant crystal control register (IRCCTRL, address 0x4004 8028) bit
description
Bit Symbol Description Reset value
7:0 TRIM Trim value 0x1000 0000, then
flash will reprogram
31:8 - Reserved 0x00