Datasheet

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User manual Rev. 12.3 — 10 June 2014 291 of 547

NXP Semiconductors

UM10398

Chapter 16: LPC111x/LPC11Cxx C_CAN controller

16.6.1.5 CAN interrupt register

If several interrupts are pending, the CAN Interrupt Register will point to the pending

interrupt with the highest priority, disregarding their chronological order. An interrupt

remains pending until the CPU has cleared it. If INTID is different from 0x0000 and IE is

set, the interrupt line to the CPU is active. The interrupt line remains active until INTID is

back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.

The Status Interrupt has the highest priority. Among the message interrupts, the Message

Object’ s interrupt priority decreases with increasing message number.

A message interrupt is cleared by clearing the Message Object’s INTPND bit. The

StatusInterrupt is cleared by reading the Status Register.

16.6.1.6 CAN test register

Write access to the Test Register is enabled by setting bit Test in the CAN Control

The different test functions may be combined, but when TX[1:0]  “00” is selected, the

message transfer is disturbed.

Table 250. CAN interrupt register (CANINT, address 0x4005 0010) bit description

Bit Symbol Description Reset

value

Access

15:0 INTID 0x0000 = No interrupt is pending.

0x0001 - 0x0020 = Number of message object which

caused the interrupt.

0x0021 - 0x7FFF = Unused

0x8000 = Status interrupt

0x8001 - 0xFFFF = Unused

31:16 - Reserved - -

Table 251. CAN test register (CANTEST, address 0x4005 0014) bit description

Bit Symbol Value Description Reset

value

Access

1:0 - - Reserved -

2 BASIC Basic mode 0 R/W

0 Disabled. Basic mode disabled.

1 Enabled. IF1 registers used as TX buffer, IF2

registers used as RX buffer.

3 SILENT Silent mode 0 R/W

0 Normal operation.

1 Silent mode. The module is in silent mode.

4 LBACK Loop back mode 0 R/W

0 Disabled. Loop back mode is disabled.

1 Enabled. Loop back mode is enabled.