Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 293 of 547
NXP Semiconductors
UM10398
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
Each set of interface registers consists of message buffer registers controlled by their own
command registers. The command mask register specifies the direction of the data
transfer and which parts of a message object will be transferred. The command request
register is used to select a message object in the message RAM as target or source for
the transfer and to start the action specified in the command mask register.
There are 32 Message Objects in the Message RAM. To avoid conflicts between CPU
access to the Message RAM and CAN message reception and transmission, the CPU
cannot directly access the Message Objects. The message objects are accessed through
the IFx Interface Registers.
For details of message handling, see Section 16.7.3
.
16.6.2.1 Message objects
A message object contains the information from the various bits in the message interface
registers. Table 254
below shows a schematic representation of the structure of the
message object. The bits of a message object and the respective interface register where
this bit is set or cleared are shown. For bit functions see the corresponding interface
register.
16.6.2.2 CAN message interface command request registers
A message transfer is started as soon as the CPU has written the message number to the
Command Request Register. With this write operation the BUSY bit is automatically set to
‘1’ and the signal CAN_WAIT_B is pulled LOW to notify the CPU that a transfer is in
progress. After a wait time of 3 to 6 CAN_CLK periods, the transfer between the Interface
Register and the Message RAM has completed. The BUSY bit is set back to zero and the
signal CAN_WAIT_B is set back.
Table 253. Message interface registers
IF1 register names IF1 register set IF2 register names IF2 register set
CANIF1_CMDREQ IF1 command request CANIF2_CMDREQ IF2 command request
CANIF1_CMDMASK IF1 command mask CANIF2_CMDMASK IF2 command mask
CANIF1_MASK1 IF1 mask 1 CANIF2_MSK1 IF2 mask 1
CANIF1_MASK2 IF1 mask 2 CANIF2_MSK2 IF2 mask 2
CANIF1_ARB1 IF1 arbitration 1 CANIF2_ARB1 IF2 arbitration 1
CANIF1_ARB2 IF1 arbitration 2 CANIF2_ARB2 IF2 arbitration 2
CANIF1_MCTRL IF1 message control CANIF2_MCTRL IF2 message control
CANIF1_DA1 IF1 data A1 CANIF2_DA1 IF2 data A1
CANIF1_DA2 IF1 data A2 CANIF2_DA2 IF2 data A2
CANIF1_DB1 IF1 data B1 CANIF2_DB1 IF2 data B1
CANIF1_DB2 IF1 data B2 CANIF2_DB2 IF2 data B2
Table 254. Structure of a message object in the message RAM
UMASK MSK[28:0] MXTD MDIR EOB NEWDAT MSGLST RXIE TXIE INTPND
IF1/2_MCTRL IF1/2_MSK1/2 IF1/2_MCTRL
RMTEN TXRQST MSGVAL ID[28:0] XTD DIR DLC3 DLC2 DLC1 DLC0
IF1/2_MCTRL IF1/2_ARB1/2 IF1/2_MCTRL
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7
IF1/2_DA1 IF1/2_DA2 IF1/2_DB1 IF1/2_DB2