Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 295 of 547
NXP Semiconductors
UM10398
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
2 TXRQST Access transmission request bit 0 R/W
0 No transmission request. TXRQST bit
unchanged in IF1/2_MCTRL.
Remark: If a transmission is requested by
programming this bit, the TXRQST bit in the
CANIFn_MCTRL register is ignored.
1 Request a transmission. Set the TXRQST bit
IF1/2_MCTRL.
3 CLRINTPND - This bit is ignored in the write direction. 0 R/W
4 CTRL Access control bits 0 R/W
0 Unchanged. Control bits unchanged.
1 Transfer. Transfer control bits to message
object
5 ARB Access arbitration bits 0 R/W
0 Unchanged. Arbitration bits unchanged.
1 Transfer. Transfer Identifier, DIR, XTD, and
MSGVAL bits to message object.
6 MASK Access mask bits 0 R/W
0 Unchanged. Mask bits unchanged.
1 Transfer. Transfer Identifier MSK + MDIR +
MXTD to message object.
7 WR_RD 1 Write transfer
Transfer data from the selected message
buffer registers to the message object
addressed by the command request register
CANIFn_CMDREQ.
0R/W
31:8 - - reserved 0 -
Table 257. CAN message interface command mask registers (CANIF1_CMDMSK_R, address
0x4005 0024 and CANIF2_CMDMSK_R, address 0x4005 0084) bit description for
read direction
Bit Symbol Value Description Reset
value
Access
0 DATA_B Access data bytes 4-7 0 R/W
0 Unchanged. Data bytes 4-7 unchanged.
1 Transfer. Transfer data bytes 4-7 to IFx
message buffer register.
1 DATA_A Access data bytes 0-3 0 R/W
0 Unchanged. Data bytes 0-3 unchanged.
1 Transfer. Transfer data bytes 0-3 to IFx
message buffer.
Table 256. CAN message interface command mask registers (CANIF1_CMDMSK_W, address
0x4005 0024 and CANIF2_CMDMSK_W, address 0x4005 0084) bit description for
write direction
…continued
Bit Symbol Value Description Reset
value
Access