Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 30 of 547
NXP Semiconductors
UM10398
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
The reset value given in Table 15 applies to the POR reset.
3.5.9 System PLL clock source select register
This register selects the clock source for the system PLL. The SYSPLLCLKUEN register
(see Section 3.5.10
) must be toggled from LOW to HIGH for the update to take effect.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
Remark: When using the C_CAN controller with baudrates above 100 kbit/s, the system
oscillator must be selected.
Table 15. System reset status register (SYSRSTSTAT, address 0x4004 8030) bit description
Bit Symbol Value Description Reset
value
0 POR POR reset status 0x0
0 No POR detected.
1 POR detected. Writing a one clears this reset.
1 EXTRST Status of the external RESET
pin. 0x0
0 No RESET
event detected.
1 RESET
detected. Writing a one clears this reset.
2 WDT Status of the Watchdog reset 0x0
0 No WDT reset detected.
1 WDT reset detected. Writing a one clears this reset.
3 BOD Status of the Brown-out detect reset 0x0
0 No BOD reset detected.
1 BOD reset detected. Writing a one clears this reset.
4 SYSRST Status of the software system reset 0x0
0 No System reset detected.
1 System reset detected. Writing a one clears this reset.
31:5 - - Reserved 0x0
Table 16. System PLL clock source select register (SYSPLLCLKSEL, address 0x4004 8040)
bit description
Bit Symbol Value Description Reset
value
1:0 SEL System PLL clock source 0x00
0x0 IRC oscillator
0x1 System oscillator
0x2 Reserved
0x3 Reserved
31:2 - - Reserved 0x00