Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 316 of 547
NXP Semiconductors
UM10398
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
16.7.4 Interrupt handling
If several interrupts are pending, the CAN Interrupt Register will point to the pending
interrupt with the highest priority, disregarding their chronological order. An interrupt
remains pending until the CPU has cleared it.
Fig 66. Reading a message from the FIFO buffer to the message buffer
START
END
read CANIR
MessageNum = INTID
read CANIFx_MCTRL
write MessageNum to CANIFx_CMDREQ
read data from CANIFx_DA/B
MessageNum = MessageNum +1
read message to message buffer
reset NEWDAT = 0
reset INTPND = 0
INTID = 0x8000 ?
NEWDAT = 1
EOB = 1
INTID = 0x0001
to 0x0020 ?
INTID = 0x0000 ?
status change
interrupt handling
yes yes
yes
yes
no
no
yes