Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 319 of 547
NXP Semiconductors
UM10398
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
16.7.5.2 Calculating the C_CAN bit rate
The C_CAN clock is derived from the system clock. The C_CAN clock can be divided by
the C_CAN clock divider (Table 1013
): CAN_CLK = system clock/ (DIVVAL +1).
Using Figure 67
and Table 278, the bit rate and sample point can be expressed as follows
using t
q
= BRP / CAN_CLK:
Bit rate = 1/(t
q
x total number of quantas) = 1 / (t
q
x (1 + PROP_SEG+TSEG1+TSEG2)) =
CAN_CLK / (BRP x (1 + PROP_SEG+TSEG1+TSEG2))
Sample point = (1 + PROP_SEG+TSEG1) / (1 + PROP_SEG+TSEG1+TSEG2) x 100
The CAN BT register (see Table 249
) stores the bit timing information for parameters BRP
(bits 5:0), PROP_SEG +TSEG1 (bits 11:8, named TSEG1), and TSEG2. Note that the
register content are +1 encoded.
Using the contents of the BT register for BRP, TSEG1, and TSEG2, the bit rate can be
calculated as follows:
Bit rate = CAN_CLK/((BRP + 1) x (TSEG1+2+TSEG2+1))
Sample point = (TSEG1+2) / (TSEG1+2+TSEG2+1) x 100
Fig 67. Bit timing
PHASE_SEG1 PHASE_SEG2
TSEG1
TSEG2