Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 333 of 547
18.1 How to read this chapter
The 16-bit timer blocks are identical for all LPC111x, LPC11D14, and LPC11Cxx parts in
the LPC1100, LPC1100C, and LPC1100L series.
Pin-out variations
The match output MAT0 of timer 1 (CT16B1_MAT0) is not pinned out on parts LPC11C22
and LPC11C24.
18.2 Basic configuration
The CT16B0/1 are configured using the following registers:
1. Pins: The CT16B0/1 pins must be configured in the IOCONFIG register block
(Section 7.4
).
2. Power and peripheral clock: In the SYSAHBCLKCTRL register, set bit 7 and bit 8
(Table 21
). The peripheral clock is provided by the system clock (see Table 20).
18.3 Features
• Two 16-bit counter/timers with a programmable 16-bit prescaler.
• Counter or timer operation.
• One 16-bit capture channel that can take a snapshot of the timer value when an input
signal transitions. A capture event may also optionally generate an interrupt.
• Four 16-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to three (CT16B0) or two (CT16B1) external outputs corresponding to match
registers with the following capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
• For each timer, up to four match registers can be configured as PWM allowing to use
up to three match outputs as single edge controlled PWM outputs.
UM10398
Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit
counter/timer CT16B0/1
Rev. 12.3 — 10 June 2014 User manual