Datasheet
UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 337 of 547
NXP Semiconductors
UM10398
Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit counter/timer
18.7.2 Timer Control Register (TMR16B0TCR and TMR16B1TCR)
The Timer Control Register (TCR) is used to control the operation of the counter/timer.
18.7.3 Timer Counter (TMR16B0TC - address 0x4000 C008 and
TMR16B1TC - address 0x4001 0008)
The 16-bit Timer Counter is incremented when the Prescale Counter reaches its terminal
count. Unless it is reset before reaching its upper limit, the TC will count up through the
value 0x0000 FFFF and then wrap back to the value 0x0000 0000. This event does not
cause an interrupt, but a Match register can be used to detect an overflow if needed.
18.7.4 Prescale Register (TMR16B0PR - address 0x4000 C00C and
TMR16B1PR - address 0x4001 000C)
The 16-bit Prescale Register specifies the maximum value for the Prescale Counter.
Table 282. Interrupt Register (TMR16B0IR - address 0x4000 C000 and TMR16B1IR - address 0x4001 0000) bit
description
Bit Symbol Description Reset value
0 MR0 Interrupt Interrupt flag for match channel 0. 0
1 MR1 Interrupt Interrupt flag for match channel 1. 0
2 MR2 Interrupt Interrupt flag for match channel 2. 0
3 MR3 Interrupt Interrupt flag for match channel 3. 0
4 CR0 Interrupt Interrupt flag for capture channel 0 event. 0
31:5 - Reserved -
Table 283. Timer Control Register (TMR16B0TCR - address 0x4000 C004 and TMR16B1TCR -
address 0x4001 0004) bit description
Bit Symbol Description Reset value
0 CEn Counter Enable. When one, the Timer Counter and
Prescale Counter are enabled for counting. When zero,
the counters are disabled.
0
1 CRst Counter Reset. When one, the Timer Counter and the
Prescale Counter are synchronously reset on the next
positive edge of PCLK. The counters remain reset until
TCR[1] is returned to zero.
0
31:2 - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
NA
Table 284: Timer counter registers (TMR16B0TC, address 0x4000 C008 and TMR16B1TC
0x4001 0008) bit description
Bit Symbol Description Reset
value
15:0 TC Timer counter value. 0
31:16 - Reserved. -