Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 34 of 547
NXP Semiconductors
UM10398
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
3.5.15 SPI0 clock divider register
This register configures the SPI0 peripheral clock SPI0_PCLK. The SPI0_PCLK can be
shut down by setting the DIV bits to 0x0.
3.5.16 UART clock divider register
This register configures the UART peripheral clock UART_PCLK. The UART_PCLK can
be shut down by setting the DIV bits to 0x0.
Remark: Note that for some parts the UART pins must be configured in the IOCON block
before the UART clock can be enabled.
See Section 3.1 for part specific details.
3.5.17 SPI1 clock divider register
This register configures the SPI1 peripheral clock SPI1_PCLK. The SPI1_PCLK can be
shut down by setting the DIV bits to 0x0.
17 CAN Enables clock for C_CAN. See Section 3.1 for part
specific details.
0
0 Disable
1 Enable
18 SSP1 Enables clock for SPI1. 0
0 Disable
1 Enable
31:19 - - Reserved 0x00
Table 21. System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit
description
…continued
Bit Symbol Value Description Reset
value
Table 22. SPI0 clock divider register (SSP0CLKDIV, address 0x4004 8094) bit description
Bit Symbol Description Reset value
7:0 DIV SPI0_PCLK clock divider values
0: Disable SPI0_PCLK.
1: Divide by 1.
to
255: Divide by 255.
0x00
31:8 - Reserved 0x00
Table 23. UART clock divider register (UARTCLKDIV, address 0x4004 8098) bit description
Bit Symbol Description Reset value
7:0 DIV UART_PCLK clock divider values
0: Disable UART_PCLK.
1: Divide by 1.
to
255: Divide by 255.
0x00
31:8 - Reserved 0x00